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Improve sim #30

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Jul 27, 2016
Merged

Improve sim #30

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57c5df1
Check jit entry per core.
Jul 27, 2016
c9b3fb3
Return correct exit code. Handle keyboard interrupts.
Jul 27, 2016
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3 changes: 3 additions & 0 deletions .coveragerc
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Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,9 @@ exclude_lines =
# Don't complain about unimplemented code:
raise NotImplementedError

# Don't complain about Ctrl+c
except KeyboardInterrupt

# Don't complain if tests take a path which is only used in a test harness:
def init_state
def iread
Expand Down
32 changes: 23 additions & 9 deletions revelation/sim.py
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Expand Up @@ -13,9 +13,15 @@

import time

EXIT_SUCCESS = 0
EXIT_GENERAL_ERROR = 1
EXIT_SYNTAX_ERROR = 2
EXIT_FILE_ERROR = 126
EXIT_CTRL_C = 130
LOG_FILENAME = 'r_trace.out'
MEMORY_SIZE = 2**32 # Global on-chip address space.


def new_memory(logger):
return MemoryFactory(size=MEMORY_SIZE, logger=logger)

Expand All @@ -32,6 +38,7 @@ def __init__(self):
reds = ['tick_counter',
'halted_cores',
'idle_cores',
'old_pcs',
'memory',
'sim',
'state',
Expand Down Expand Up @@ -86,23 +93,26 @@ def entry_point(argv):
try:
fname, jit, flags = cli_parser(argv, self, Debug.global_enabled)
except DoNotInterpretError: # CLI option such as --help or -h.
return 0
return EXIT_SUCCESS
except (SyntaxError, ValueError):
return 1
return EXIT_SYNTAX_ERROR
if jit: # pragma: no cover
set_user_param(self.jitdriver, jit)
self.debug = Debug(flags, 0)
try:
elf_file = open(fname, 'rb')
except IOError:
print 'Could not open file %s' % fname
return 1
return EXIT_FILE_ERROR
self.init_state(elf_file, fname, False)
for state in self.states: # FIXME: Interleaved log.
self.debug.set_state(state)
elf_file.close()
self.run()
return 0
try:
exit_code = self.run()
except KeyboardInterrupt:
return EXIT_CTRL_C
return exit_code
return entry_point

def decode(self, bits):
Expand Down Expand Up @@ -178,7 +188,7 @@ def run(self):
memory = hint(self.memory, promote=True) # Cores share the same memory.
tick_counter = 0 # Number of instructions executed by all cores.
halted_cores, idle_cores = [], []
old_pc = 0
old_pcs = [0] * len(self.states)
start_time, end_time = time.time(), .0

while True:
Expand All @@ -187,13 +197,14 @@ def run(self):
tick_counter=tick_counter,
halted_cores=halted_cores,
idle_cores=idle_cores,
old_pcs=old_pcs,
memory=memory,
sim=self,
state=self.states[self.core],
start_time=start_time)
# Fetch PC, decode instruction and execute.
pc = hint(self.states[self.core].fetch_pc(), promote=True)
old_pc = pc
old_pcs[self.core] = pc
inst_bits = memory.iread(pc, 4, from_core=self.states[self.core].coreid)
try:
instruction, exec_fun = self.decode(inst_bits)
Expand All @@ -203,7 +214,8 @@ def run(self):
except FatalError as error:
print 'Exception in execution (pc: 0x%s), aborting!' % pad_hex(pc)
print 'Exception message: %s' % error.msg
break # pragma: no cover
# Ensure that entry_point() returns correct exit code.
return EXIT_GENERAL_ERROR # pragma: no cover
# Update instruction counters.
tick_counter += 1
self.states[self.core].num_insts += 1
Expand All @@ -228,12 +240,13 @@ def run(self):
elif (self.core in idle_cores and self.fetch_latch() > 0):
idle_cores.remove(self.core)
self._service_interrupts()
if old_pc < self.states[self.core].fetch_pc(): # TODO: old_pc per core?
if self.states[self.core].fetch_pc() < old_pcs[self.core]:
self.jitdriver.can_enter_jit(pc=self.states[self.core].fetch_pc(),
core=self.core,
tick_counter=tick_counter,
halted_cores=halted_cores,
idle_cores=idle_cores,
old_pcs=old_pcs,
memory=memory,
sim=self,
state=self.states[self.core],
Expand All @@ -250,6 +263,7 @@ def run(self):
print 'Total execution time: %fs' % (end_time - start_time)
if self.logger:
self.logger.close()
return EXIT_SUCCESS

def init_state(self, elf_file, filename, testbin, is_test=False):
"""Revelation has custom logging infrastructure that differs from the
Expand Down