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Update vhdl-ts-mode package.el unit test
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@gmlarumbe
gmlarumbe committed Sep 7, 2023
1 parent b3a9da6 commit 146b80e
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Showing 3 changed files with 2 additions and 3 deletions.
2 changes: 1 addition & 1 deletion .github/workflows/build_package.yml
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Expand Up @@ -33,4 +33,4 @@ jobs:
- name: Run ERT tests
run: |
make PKG_MANAGER=package
make pkg_el
1 change: 0 additions & 1 deletion Makefile
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Expand Up @@ -12,6 +12,5 @@ TEST_HDL_PATH = test-hdl
ERT_TESTS = $(TEST_HDL_PATH)/ert-tests.sh
LANGUAGE = vhdl
PACKAGE = vhdl-ts-mode
PKG_MANAGER ?= straight

include $(TEST_HDL_PATH)/Makefile.mk
2 changes: 1 addition & 1 deletion test-hdl
Submodule test-hdl updated 79 files
+6 −10 Makefile.mk
+30 −17 ert-tests.sh
+12 −5 test-hdl-common.el
+6 −0 test-hdl.el
+11 −2 verilog/test-hdl-verilog-beautify.el
+10 −1 verilog/test-hdl-verilog-common.el
+1 −1 verilog/test-hdl-verilog-faceup.el
+1 −1 verilog/test-hdl-verilog-imenu.el
+2 −3 verilog/test-hdl-verilog-indent.el
+1 −1 verilog/test-hdl-verilog-navigation.el
+1 −2 verilog/test-hdl-verilog-utils.el
+52 −0 verilog/verilog-ext/test-hdl-verilog-ext-hierarchy.el
+3 −5 verilog/verilog-ts-mode/test-hdl-verilog-ts-mode-beautify.el
+54 −0 verilog/verilog-ts-mode/test-hdl-verilog-ts-mode-setup-package.el
+73 −0 verilog/verilog-ts-mode/test-hdl-verilog-ts-mode-setup-straight.el
+1 −1 verilog/verilog-ts-mode/test-hdl-verilog-ts-mode.el
+37 −0 vhdl/files/axi_if_converter/rtl/BUFG.vhd
+810 −0 vhdl/files/axi_if_converter/rtl/axi_if_converter.vhd
+266 −0 vhdl/files/axi_if_converter/rtl/axi_lite_master.vhd
+617 −0 vhdl/files/axi_if_converter/rtl/axi_lite_regs.vhd
+69 −0 vhdl/files/axi_if_converter/rtl/clk_div.vhd
+59 −0 vhdl/files/axi_if_converter/rtl/clk_sync.vhd
+821 −0 vhdl/files/axi_if_converter/rtl/core_converter.vhd
+155 −0 vhdl/files/axi_if_converter/rtl/core_fsm.vhd
+81 −0 vhdl/files/axi_if_converter/rtl/global_pkg.vhd
+586 −0 vhdl/files/axi_if_converter/rtl/input_buffer.vhd
+128 −0 vhdl/files/axi_if_converter/rtl/input_buffer_pkg.vhd
+73 −0 vhdl/files/axi_if_converter/rtl/pattern_counter.vhd
+120 −0 vhdl/files/axi_if_converter/tb/axif_master_bfm.vhd
+119 −0 vhdl/files/axi_if_converter/tb/axil_master_bfm.vhd
+138 −0 vhdl/files/axi_if_converter/tb/axil_slave_bfm.vhd
+2,988 −0 vhdl/files/axi_if_converter/tb/blk_mem_gen_0_netlist.vhd
+286 −0 vhdl/files/axi_if_converter/tb/global_sim.vhd
+424 −0 vhdl/files/axi_if_converter/tb/s_axi_model.vhd
+607 −0 vhdl/files/axi_if_converter/tb/tb_axi_if_converter.vhd
+238 −0 vhdl/files/axi_if_converter/tb/tb_axi_lite_master.vhd
+261 −0 vhdl/files/axi_if_converter/tb/tb_axi_lite_regs.vhd
+632 −0 vhdl/files/axi_if_converter/tb/tb_core_converter.vhd
+209 −0 vhdl/files/axi_if_converter/tb/tb_core_fsm.vhd
+320 −0 vhdl/files/axi_if_converter/tb/tb_input_buffer.vhd
+133 −0 vhdl/files/axi_if_converter/tb/tb_pattern_counter.vhd
+19 −0 vhdl/files/hierarchy/vhdl-ext/ref/axi_if_converter.builtin.hier.el
+28 −0 vhdl/files/hierarchy/vhdl-ext/ref/axi_if_converter.builtin.outshine.vhd
+335 −0 vhdl/files/hierarchy/vhdl-ext/ref/axi_if_converter.ts.hier.el
+344 −0 vhdl/files/hierarchy/vhdl-ext/ref/axi_if_converter.ts.outshine.vhd
+22 −0 vhdl/files/hierarchy/vhdl-ext/ref/hierarchy.builtin.hier.el
+31 −0 vhdl/files/hierarchy/vhdl-ext/ref/hierarchy.builtin.outshine.vhd
+338 −0 vhdl/files/hierarchy/vhdl-ext/ref/hierarchy.ts.hier.el
+347 −0 vhdl/files/hierarchy/vhdl-ext/ref/hierarchy.ts.outshine.vhd
+8 −0 vhdl/files/hierarchy/vhdl-ext/ref/instances.builtin.hier.el
+17 −0 vhdl/files/hierarchy/vhdl-ext/ref/instances.builtin.outshine.vhd
+15 −0 vhdl/files/hierarchy/vhdl-ext/ref/instances.ghdl.hier.el
+24 −0 vhdl/files/hierarchy/vhdl-ext/ref/instances.ghdl.outshine.vhd
+8 −0 vhdl/files/hierarchy/vhdl-ext/ref/instances.ts.hier.el
+17 −0 vhdl/files/hierarchy/vhdl-ext/ref/instances.ts.outshine.vhd
+22 −0 vhdl/files/hierarchy/vhdl-ext/ref/tb_axi_if_converter.builtin.hier.el
+31 −0 vhdl/files/hierarchy/vhdl-ext/ref/tb_axi_if_converter.builtin.outshine.vhd
+36 −0 vhdl/files/hierarchy/vhdl-ext/ref/tb_axi_if_converter.ghdl.hier.el
+45 −0 vhdl/files/hierarchy/vhdl-ext/ref/tb_axi_if_converter.ghdl.outshine.vhd
+338 −0 vhdl/files/hierarchy/vhdl-ext/ref/tb_axi_if_converter.ts.hier.el
+347 −0 vhdl/files/hierarchy/vhdl-ext/ref/tb_axi_if_converter.ts.outshine.vhd
+1 −1 vhdl/scripts/setup-env.sh
+13 −1 vhdl/test-hdl-vhdl-common.el
+1 −1 vhdl/test-hdl-vhdl-faceup.el
+1 −1 vhdl/test-hdl-vhdl-imenu.el
+1 −1 vhdl/test-hdl-vhdl-indent.el
+2 −2 vhdl/test-hdl-vhdl-navigation.el
+3 −4 vhdl/test-hdl-vhdl-utils.el
+1 −0 vhdl/vhdl-ext/test-hdl-vhdl-ext-beautify.el
+319 −111 vhdl/vhdl-ext/test-hdl-vhdl-ext-hierarchy.el
+1 −1 vhdl/vhdl-ext/test-hdl-vhdl-ext-navigation.el
+20 −14 vhdl/vhdl-ext/test-hdl-vhdl-ext-setup-package.el
+13 −23 vhdl/vhdl-ext/test-hdl-vhdl-ext-setup-straight.el
+3 −2 vhdl/vhdl-ext/test-hdl-vhdl-ext-tags.el
+3 −3 vhdl/vhdl-ext/test-hdl-vhdl-ext.el
+5 −7 vhdl/vhdl-ts-mode/test-hdl-vhdl-ts-mode-beautify.el
+54 −0 vhdl/vhdl-ts-mode/test-hdl-vhdl-ts-mode-setup-package.el
+73 −0 vhdl/vhdl-ts-mode/test-hdl-vhdl-ts-mode-setup-straight.el
+1 −1 vhdl/vhdl-ts-mode/test-hdl-vhdl-ts-mode.el

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