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cycleclock: Fix type conversion to match function return type on riscv64 #1802

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merged 1 commit into from
Jun 11, 2024

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kraj
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@kraj kraj commented Jun 11, 2024

Fixes builds with clang

src/cycleclock.h:213:10: error: implicit conversion changes signedness: 'uint64_t' (aka 'unsigned long') to 'int64_t' (aka 'long') [-Werror,-Wsign-conversion]
213 | return cycles;
| ~~~~~~ ^~~~~~
1 error generated.

Fixes builds with clang

src/cycleclock.h:213:10: error: implicit conversion changes signedness: 'uint64_t' (aka 'unsigned long') to 'int64_t' (aka 'long') [-Werror,-Wsign-conversion]
     213 |   return cycles;
         |   ~~~~~~ ^~~~~~
   1 error generated.
@@ -210,7 +210,7 @@ inline BENCHMARK_ALWAYS_INLINE int64_t Now() {
#else
uint64_t cycles;
asm volatile("rdtime %0" : "=r"(cycles));
return cycles;
return static_cast<int64_t>(cycles);
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maybe we should check the range before the cast?

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We don't do that anywhere else though. I'm not sure what we would even do in that situation?

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assert i guess? the C++ style guide talks about this a bit in discussing avoidance of unsigned types ("In particular, do not use unsigned types to say a number will never be negative. Instead, use assertions for this.")

but i agree we don't currently do it anywhere else. happy to punt this to another PR.

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https://riscv.org/wp-content/uploads/2016/06/riscv-spec-v2.1.pdf, page 32:

The RDTIME pseudo-instruction reads the low XLEN bits of the time CSR, which counts wall-clock
real time that has passed from an arbitrary start time in the past. RDTIMEH is an RV32I-only instruction that reads bits 63–32 of the same real-time counter. The underlying 64-bit counter should
never overflow in practice.

At 10GHz clock rate, it would take ~30 years of uptime to overflow.

@dmah42 dmah42 merged commit 8e1823d into google:main Jun 11, 2024
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dmah42 commented Jun 11, 2024

thanks!

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3 participants