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[keyword] Verible breaks when parsing a function that is defining “new” #44

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msfschaffner opened this issue Nov 26, 2019 · 5 comments
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formatter Verilog code formatter issues

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@msfschaffner
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The following code causes verible to throw an error and stop processing.

`ifndef uvm_component_new
  `define uvm_component_new \
    function new (string name="", uvm_component parent=null); \
      super.new(name, parent); \
    endfunction : new
`endif

The associated error message is:

Mismatch in token sequence lengths: 693 vs. 744
First mismatched token [69]: ("<<`define-tokens>>") (#261: "\
    function new (string name=""); \
      super.new(name); \
    endfunction : new") vs. ("<<`define-tokens>>") (#261: "")
Formatted output is lexically different from the input.  Please file go/verilogformat-bug.
Error lex/parsing-ing formatted output.  Please file go/verilogformat-bug.
First error: token: "new" at 43:14-16
@msfschaffner
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b/145170433

@fangism fangism added the formatter Verilog code formatter issues label Nov 26, 2019
@fangism
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fangism commented Nov 26, 2019

This is a bug in the formatter's output verification logic. And fail-safe behavior make it leave the original input untouched.

@tgorochowik tgorochowik self-assigned this Mar 18, 2020
@tgorochowik
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I think this issue may have been already fixed. I cannot reproduce it anymore, but it is easily reproducible by checking out code from November.

@msfschaffner could you please confirm that?

@msfschaffner
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Confirmed, this particular instance does not seem to produce issues anymore. But I found another issue in the same file (there are tons of DV macros in there). I'll spin that out as a separate issue.

@fangism
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fangism commented Apr 1, 2020

Thanks for the update and opening a new issue.

@fangism fangism closed this as completed Apr 1, 2020
nikhiljha pushed a commit to nikhiljha/verible that referenced this issue Sep 27, 2022
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Labels
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