Implement NXP's recommended PLL setup sequence.

[martinling]

This follows the sequence described in:
UM10503 Rev 2.4 (Aug 2018), section 13.2.1.1, page 167

This sequence has already been used successfully in greatscottgadgets/hackrf#1106.

The HackRF implementation uses a fixed 204 MHz configuration. In libgreat, the CPU clock configuration can be modified by redefining the weakly-linked platform_clock_source_configurations structure.

This implementation continues to support alternative CPU clock configurations, but restricts the possible CPU clock speeds to either <= 110 MHz or 180-204 MHz when running from PLL1. This is because the CPU must first run at the mid-range of 90-110 MHz for 50us before running above 110MHz, and the recommended technique of doubling the PLL to transition from the mid to high range cannot be applied for frequencies between 110 and 180 MHz.

If unsupported frequencies are specified or the PLL fails to lock, errors will be reported and the system will fall back to the internal oscillator.

[antoinevg]

Very clean, looks good to me.