Verilog Techinal Standard

picture2pixel module is a Verilog design intended to drive an OLED display using a Basys 3 FPGA board. This design involves generating different clock signals to control the frame rate and pixel sampling for the display.

Top module: picture2pixel

Contains two parameters: clk(one bit input for clock signal) and JB(eight bit output for oled parameter).

Module Functions

module picture2pixel(input clk, output [7:0] JB);
    parameter basys3_clk_freq = 100_000_000;
    parameter frame_rate = 12;
    
    wire [31:0] clk_param;
    
    wire frame_begin, sending_pixels, sample_pixel;
    
    wire [12:0] pixel_index_JB;
    wire [15:0] oled_data_JB;
    
    wire clk_25M, clk_6p25M, clk_frameRate;
    
    reg reset = 0;
    
    assign clk_param = (basys3_clk_freq / (frame_rate)) - 1;
    
    flexible_clock_signal clk25M (clk, 1, clk_25M);
    flexible_clock_signal clk6p25M (clk, 7, clk_6p25M);
    flexible_clock_signal clkframeRate (clk, clk_param, clk_frameRate);
    
    Oled_Display oledDisplay_JB (clk_6p25M, reset, frame_begin, sending_pixels, sample_pixel,
                                 pixel_index_JB, oled_data_JB, 
                                 JB[0], JB[1], JB[3], JB[4],JB[5], JB[6], JB[7]);
    
    frame_data framedata (clk_frameRate, pixel_index_JB, oled_data_JB);
endmodule

Detailed Implementation

flexible_clock_signal

Refer to the flexible_clock_signal module for detailed implementation.

Oled_Display

Refer to the website for detailed implementation.

frame_data

Refer to the frame_data for detailed implementation.

module variable declaration

parameter basys3_clk_freq = 100_000_000;
parameter frame_rate = 12;
   
wire [31:0] clk_param;
  
wire frame_begin, sending_pixels, sample_pixel;

wire [12:0] pixel_index_JB;
wire [15:0] oled_data_JB;
  
wire clk_25M, clk_6p25M, clk_frameRate;
  
reg reset = 0;

• Wires:
  • clk_param: Calculated parameter for the frame rate clock divider.
  • frame_begin, sending_pixels, sample_pixel: Control signals for the OLED display.
  • pixel_index_JB: Index of the current pixel being processed.
  • oled_data_JB: Data for the current pixel.
  • clk_25M, clk_6p25M, clk_frameRate: Derived clock signals at different frequencies.
• Registers:
• reset: Reset signal for the OLED display.

Clock Parameter Calculation

assign clk_param = (basys3_clk_freq / (frame_rate)) - 1;

flexible_clock_signal module

Module Functions

module flexible_clock_signal(input clk, input [31:0] number, output reg slw_clk = 0);

    reg [31:0] count = 0;
    always @ (posedge clk)begin
        count <= (count == number) ? 0 : count + 1;
        slw_clk <= (count == 0) ? ~slw_clk : slw_clk;
    end

endmodule

Detailed Implementation

Description

This Verilog module, flexible_clock_signal, generates a slower clock signal (slw_clk) based on an input clock (clk) and a specified count value as (number). The slower clock signal toggles its state after the input clock has cycled a specified number of times.

Ports

• Inputs:

  • clk (input): The input clock signal.
  • number (input [31:0]): A 32-bit value that determines the frequency division factor.

• Output:

  • slw_clk (output reg): The slower clock signal generated by the module.

Internal Variables

count (reg [31:0]): A 32-bit register to count the number of clock cycles.

frame_data module

Module Functions

module frame_data(input frame_rate, input [12:0] pixel_index, output reg [15:0] oled_data);
    reg [15:0] frame_count = 0;
    parameter picture_total_count = 3;
    
    always @ (posedge frame_rate) begin
        frame_count <= (frame_count == picture_total_count - 1) ? 0 : frame_count + 1;
    end
   
    always @ (*) begin
    // Put your .p2p file here ^_^   
    end

endmodule

Detailed Implementation

Ports

• Inputs:

  • frame_rate: This signal drives the frame update rate.
  • [12:0] pixel_index: This 13-bit input specifies the index of the pixel currently being addressed.

• Outputs:

  • reg [15:0] oled_data: This 16-bit register holds the output data for the OLED display.

Internal Registers

reg [15:0] frame_count: A 16-bit register to keep track of the current frame. It is initialized to 0.

Parameters

parameter picture_total_count = 3: This parameter defines the total number of frames to cycle through.

Always Block for Frame Counting

The first always block is triggered on the positive edge of the frame_rate signal. This block is responsible for updating the frame_count register.

Sammple Usage

module frame_data(input frame_rate, input [12:0] pixel_index, output reg [15:0] oled_data);
    reg [15:0] frame_count = 0;
    parameter picture_total_count = 3;
    
    always @ (posedge frame_rate) begin
        frame_count <= (frame_count == picture_total_count - 1) ? 0 : frame_count + 1;
    end
   
    always @ (*) begin
    /*
    if (frame_count == 0) begin
        //Put .p2p file for the first frame
    end else if (frame_count == 1) begin
        //Put .p2p file for the second frame
    end else if (frame_count == 2) begin
        //Put .p2p file for the third frame
    end ........................
    */
    end

endmodule