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[Hexagon] Remove v62 support #7608

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[Hexagon] Remove v62 support #7608

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ffb5c51
[Hexagon] Remove v62 support
aankit-quic Jun 2, 2023
7393635
Run clang-format
aankit-quic Jun 2, 2023
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2 changes: 0 additions & 2 deletions python_bindings/src/halide/halide_/PyEnums.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -142,8 +142,6 @@ void define_enums(py::module &m) {
.value("LargeBuffers", Target::Feature::LargeBuffers)
.value("HVX", Target::Feature::HVX)
.value("HVX_128", Target::Feature::HVX_128)
.value("HVX_v62", Target::Feature::HVX_v62)
.value("HVX_v65", Target::Feature::HVX_v65)
.value("HVX_v66", Target::Feature::HVX_v66)
.value("FuzzFloatStores", Target::Feature::FuzzFloatStores)
.value("SoftFloatABI", Target::Feature::SoftFloatABI)
Expand Down
61 changes: 20 additions & 41 deletions src/CodeGen_Hexagon.cpp
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Expand Up @@ -54,10 +54,6 @@ class CodeGen_Hexagon : public CodeGen_Posix {
std::vector<Type> arg_types,
int flags);

int is_hvx_v65_or_later() const {
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@aankit-ca - where is hvx_v66 needed? I dont see any use of anything that is available at v66 but not v65, but I may be mistaken.

return (isa_version >= 65);
}

using CodeGen_Posix::visit;

/** Nodes for which we want to emit specific hexagon intrinsics */
Expand Down Expand Up @@ -130,10 +126,8 @@ CodeGen_Hexagon::CodeGen_Hexagon(const Target &t)
: CodeGen_Posix(t) {
if (target.has_feature(Halide::Target::HVX_v66)) {
isa_version = 66;
} else if (target.has_feature(Halide::Target::HVX_v65)) {
isa_version = 65;
} else {
isa_version = 62;
isa_version = 65;
}
user_assert(target.has_feature(Target::HVX))
<< "Creating a Codegen target for Hexagon without the hvx target feature.\n";
Expand Down Expand Up @@ -484,13 +478,11 @@ void CodeGen_Hexagon::compile_func(const LoweredFunc &f,
debug(2) << "Hexagon: Lowering after unpredicating loads/stores:\n"
<< body << "\n\n";

if (is_hvx_v65_or_later()) {
// Generate vscatter-vgathers before optimize_hexagon_shuffles.
debug(1) << "Hexagon: Looking for vscatter-vgather...\n";
body = scatter_gather_generator(body);
debug(2) << "Hexagon: Lowering after vscatter-vgather:\n"
<< body << "\n\n";
}
// Generate vscatter-vgathers before optimize_hexagon_shuffles.
debug(1) << "Hexagon: Looking for vscatter-vgather...\n";
body = scatter_gather_generator(body);
debug(2) << "Hexagon: Lowering after vscatter-vgather:\n"
<< body << "\n\n";

debug(1) << "Hexagon: Optimizing shuffles...\n";
// vlut always indexes 64 bytes of the LUT at a time, even in 128 byte mode.
Expand Down Expand Up @@ -537,7 +529,6 @@ struct HvxIntrinsic {
enum {
BroadcastScalarsToWords = 1 << 0, // Some intrinsics need scalar arguments
// broadcasted up to 32 bits.
v65OrLater = 1 << 1,
};
llvm::Intrinsic::ID id;
halide_type_t ret_type;
Expand Down Expand Up @@ -664,7 +655,7 @@ const HvxIntrinsic intrinsic_wrappers[] = {
// Absolute value:
{INTRINSIC_128B(vabsh), u16v1, "abs.vh", {i16v1}},
{INTRINSIC_128B(vabsw), u32v1, "abs.vw", {i32v1}},
{INTRINSIC_128B(vabsb), u8v1, "abs.vb", {i8v1}, HvxIntrinsic::v65OrLater},
{INTRINSIC_128B(vabsb), u8v1, "abs.vb", {i8v1}},

// Absolute difference:
{INTRINSIC_128B(vabsdiffub), u8v1, "absd.vub.vub", {u8v1, u8v1}},
Expand All @@ -675,21 +666,21 @@ const HvxIntrinsic intrinsic_wrappers[] = {
// Averaging:
{INTRINSIC_128B(vavgub), u8v1, "avg.vub.vub", {u8v1, u8v1}},
{INTRINSIC_128B(vavguh), u16v1, "avg.vuh.vuh", {u16v1, u16v1}},
{INTRINSIC_128B(vavguw), u32v1, "avg.vuw.vuw", {u32v1, u32v1}, HvxIntrinsic::v65OrLater},
{INTRINSIC_128B(vavgb), i8v1, "avg.vb.vb", {i8v1, i8v1}, HvxIntrinsic::v65OrLater},
{INTRINSIC_128B(vavguw), u32v1, "avg.vuw.vuw", {u32v1, u32v1}},
{INTRINSIC_128B(vavgb), i8v1, "avg.vb.vb", {i8v1, i8v1}},
{INTRINSIC_128B(vavgh), i16v1, "avg.vh.vh", {i16v1, i16v1}},
{INTRINSIC_128B(vavgw), i32v1, "avg.vw.vw", {i32v1, i32v1}},

{INTRINSIC_128B(vavgubrnd), u8v1, "avg_rnd.vub.vub", {u8v1, u8v1}},
{INTRINSIC_128B(vavguhrnd), u16v1, "avg_rnd.vuh.vuh", {u16v1, u16v1}},
{INTRINSIC_128B(vavguwrnd), u32v1, "avg_rnd.vuw.vuw", {u32v1, u32v1}, HvxIntrinsic::v65OrLater},
{INTRINSIC_128B(vavgbrnd), i8v1, "avg_rnd.vb.vb", {i8v1, i8v1}, HvxIntrinsic::v65OrLater},
{INTRINSIC_128B(vavguwrnd), u32v1, "avg_rnd.vuw.vuw", {u32v1, u32v1}},
{INTRINSIC_128B(vavgbrnd), i8v1, "avg_rnd.vb.vb", {i8v1, i8v1}},
{INTRINSIC_128B(vavghrnd), i16v1, "avg_rnd.vh.vh", {i16v1, i16v1}},
{INTRINSIC_128B(vavgwrnd), i32v1, "avg_rnd.vw.vw", {i32v1, i32v1}},

// This one is weird: i8_sat((u8 - u8)/2). It both saturates and averages.
{INTRINSIC_128B(vnavgub), i8v1, "navg.vub.vub", {u8v1, u8v1}},
{INTRINSIC_128B(vnavgb), i8v1, "navg.vb.vb", {i8v1, i8v1}, HvxIntrinsic::v65OrLater},
{INTRINSIC_128B(vnavgb), i8v1, "navg.vb.vb", {i8v1, i8v1}},
{INTRINSIC_128B(vnavgh), i16v1, "navg.vh.vh", {i16v1, i16v1}},
{INTRINSIC_128B(vnavgw), i32v1, "navg.vw.vw", {i32v1, i32v1}},

Expand Down Expand Up @@ -805,7 +796,7 @@ const HvxIntrinsic intrinsic_wrappers[] = {
// Rounding shift right
{INTRINSIC_128B(vasrhubrndsat), u8v1, "trunc_satub_shr_rnd.vh", {i16v2, u16}},
{INTRINSIC_128B(vasrhbrndsat), i8v1, "trunc_satb_shr_rnd.vh", {i16v2, u16}},
{INTRINSIC_128B(vasruhubrndsat), u8v1, "trunc_satub_shr_rnd.vuh", {u16v2, u16}, HvxIntrinsic::v65OrLater},
{INTRINSIC_128B(vasruhubrndsat), u8v1, "trunc_satub_shr_rnd.vuh", {u16v2, u16}},
{INTRINSIC_128B(vasrwuhrndsat), u16v1, "trunc_satuh_shr_rnd.vw", {i32v2, u32}},
{INTRINSIC_128B(vasrwhrndsat), i16v1, "trunc_sath_shr_rnd.vw", {i32v2, u32}},
{INTRINSIC_128B(vasruwuhrndsat), u16v1, "trunc_satuh_shr_rnd.vuw", {u32v2, u32}},
Expand All @@ -824,8 +815,8 @@ const HvxIntrinsic intrinsic_wrappers[] = {
{INTRINSIC_128B(vaslw), u32v1, "shl.vuw.w", {u32v1, u32}},
{INTRINSIC_128B(vaslh), i16v1, "shl.vh.h", {i16v1, u16}},
{INTRINSIC_128B(vaslw), i32v1, "shl.vw.w", {i32v1, u32}},
{INTRINSIC_128B(vasrh_acc), i16v1, "add_shr.vh.vh.uh", {i16v1, i16v1, i16}, HvxIntrinsic::BroadcastScalarsToWords | HvxIntrinsic::v65OrLater},
{INTRINSIC_128B(vaslh_acc), i16v1, "add_shl.vh.vh.uh", {i16v1, i16v1, i16}, HvxIntrinsic::BroadcastScalarsToWords | HvxIntrinsic::v65OrLater},
{INTRINSIC_128B(vasrh_acc), i16v1, "add_shr.vh.vh.uh", {i16v1, i16v1, i16}, HvxIntrinsic::BroadcastScalarsToWords},
{INTRINSIC_128B(vaslh_acc), i16v1, "add_shl.vh.vh.uh", {i16v1, i16v1, i16}, HvxIntrinsic::BroadcastScalarsToWords},
{INTRINSIC_128B(vasrw_acc), i32v1, "add_shr.vw.vw.uw", {i32v1, i32v1, i32}},
{INTRINSIC_128B(vaslw_acc), i32v1, "add_shl.vw.vw.uw", {i32v1, i32v1, i32}},

Expand Down Expand Up @@ -886,11 +877,6 @@ llvm::Function *CodeGen_Hexagon::define_hvx_intrinsic(llvm::Function *intrin,
internal_assert(intrin) << "Null definition for intrinsic '" << name << "'\n";
llvm::FunctionType *intrin_ty = intrin->getFunctionType();
bool broadcast_scalar_word = flags & HvxIntrinsic::BroadcastScalarsToWords;
bool v65OrLater = flags & HvxIntrinsic::v65OrLater;

if (v65OrLater && !is_hvx_v65_or_later()) {
return nullptr;
}

// Get the types of the arguments we want to pass.
vector<llvm::Type *> llvm_arg_types;
Expand Down Expand Up @@ -1789,10 +1775,8 @@ Value *CodeGen_Hexagon::call_intrin(llvm::Type *result_type, const string &name,
string CodeGen_Hexagon::mcpu_target() const {
if (target.has_feature(Halide::Target::HVX_v66)) {
return "hexagonv66";
} else if (target.has_feature(Halide::Target::HVX_v65)) {
return "hexagonv65";
} else {
return "hexagonv62";
return "hexagonv65";
}
}

Expand Down Expand Up @@ -1923,12 +1907,10 @@ void CodeGen_Hexagon::visit(const Call *op) {
internal_assert(op->args.size() == 1);
Type ty = op->args[0].type();
if ((ty.is_vector() && ty.is_int())) {
if (ty.bits() != 8 || is_hvx_v65_or_later()) {
value = call_intrin(op->type,
"halide.hexagon.abs" + type_suffix(op->args[0]),
op->args);
return;
}
value = call_intrin(op->type,
"halide.hexagon.abs" + type_suffix(op->args[0]),
op->args);
return;
}
} else if (op->is_intrinsic(Call::cast_mask)) {
internal_error
Expand Down Expand Up @@ -2252,9 +2234,6 @@ void CodeGen_Hexagon::visit(const Allocate *alloc) {
}
} else if (alloc->memory_type == MemoryType::VTCM &&
!alloc->new_expr.defined()) {
if (!is_hvx_v65_or_later()) {
user_error << "VTCM store_in requires HVX_v65 or later.\n";
}
// Calculate size of allocation.
Expr size = alloc->type.bytes();
for (const auto &extent : alloc->extents) {
Expand Down
10 changes: 3 additions & 7 deletions src/HexagonOffload.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,8 @@ enum {
EF_HEXAGON_MACH_V5 = 0x4,
EF_HEXAGON_MACH_V55 = 0x5,
EF_HEXAGON_MACH_V60 = 0x60, // Deprecated
EF_HEXAGON_MACH_V61 = 0x61, // Deprecated?
EF_HEXAGON_MACH_V62 = 0x62,
EF_HEXAGON_MACH_V61 = 0x61, // Deprecated
EF_HEXAGON_MACH_V62 = 0x62, // Deprecated
EF_HEXAGON_MACH_V65 = 0x65,
EF_HEXAGON_MACH_V66 = 0x66,
};
Expand Down Expand Up @@ -553,10 +553,8 @@ class HexagonLinker : public Linker {
HexagonLinker(const Target &target) {
if (target.has_feature(Target::HVX_v66)) {
flags = Elf::EF_HEXAGON_MACH_V66;
} else if (target.has_feature(Target::HVX_v65)) {
flags = Elf::EF_HEXAGON_MACH_V65;
} else {
flags = Elf::EF_HEXAGON_MACH_V62;
flags = Elf::EF_HEXAGON_MACH_V65;
}
}

Expand Down Expand Up @@ -980,8 +978,6 @@ Stmt inject_hexagon_rpc(Stmt s, const Target &host_target,
Target::Profile,
Target::NoAsserts,
Target::HVX_128,
Target::HVX_v62,
Target::HVX_v65,
Target::HVX_v66,
};
for (Target::Feature i : shared_features) {
Expand Down
19 changes: 7 additions & 12 deletions src/HexagonOptimize.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -184,7 +184,6 @@ struct Pattern {
// re-interleave the result.
ReinterleaveOp0 = InterleaveResult | DeinterleaveOp0,

v65orLater = 1 << 10, // Pattern should be matched only for v65 target or later
v66orLater = 1 << 11, // Pattern should be matched only for v66 target or later
};

Expand Down Expand Up @@ -218,10 +217,6 @@ Expr wild_i64x = Variable::make(Type(Type::Int, 64, 0), "*");

// Check if a pattern with flags 'flags' is supported on the target.
bool check_pattern_target(int flags, const Target &target) {
if ((flags & (Pattern::v65orLater)) &&
!target.features_any_of({Target::HVX_v65, Target::HVX_v66})) {
return false;
}
if ((flags & (Pattern::v66orLater)) &&
!target.features_any_of({Target::HVX_v66})) {
return false;
Expand Down Expand Up @@ -697,11 +692,11 @@ class OptimizePatterns : public IRMutator {
{"halide.hexagon.add_shr.vw.vw.uw", wild_i32x + (wild_i32x >> wild_u32)},
{"halide.hexagon.add_shl.vw.vw.uw", wild_i32x + (wild_i32x << wild_u32)},
{"halide.hexagon.add_shl.vw.vw.uw", wild_u32x + (wild_u32x << wild_u32)},
{"halide.hexagon.add_shl.vh.vh.uh", wild_i16x + (wild_i16x << wild_u16), Pattern::v65orLater},
{"halide.hexagon.add_shl.vh.vh.uh", wild_u16x + (wild_u16x << wild_u16), Pattern::v65orLater},
{"halide.hexagon.add_shr.vh.vh.uh", wild_i16x + (wild_i16x >> wild_u16), Pattern::v65orLater},
{"halide.hexagon.add_shl.vh.vh.uh", wild_i16x + (wild_i16x << wild_i16), Pattern::v65orLater},
{"halide.hexagon.add_shl.vh.vh.uh", wild_u16x + (wild_u16x << wild_u16), Pattern::v65orLater},
{"halide.hexagon.add_shl.vh.vh.uh", wild_i16x + (wild_i16x << wild_u16)},
{"halide.hexagon.add_shl.vh.vh.uh", wild_u16x + (wild_u16x << wild_u16)},
{"halide.hexagon.add_shr.vh.vh.uh", wild_i16x + (wild_i16x >> wild_u16)},
{"halide.hexagon.add_shl.vh.vh.uh", wild_i16x + (wild_i16x << wild_i16)},
{"halide.hexagon.add_shl.vh.vh.uh", wild_u16x + (wild_u16x << wild_u16)},

// Non-widening multiply-accumulates with a scalar.
{"halide.hexagon.add_mul.vh.vh.b", wild_i16x + widen_right_mul(wild_i16x, wild_i8)},
Expand Down Expand Up @@ -892,7 +887,7 @@ class OptimizePatterns : public IRMutator {
// Saturating narrowing casts with rounding
{"halide.hexagon.trunc_satub_shr_rnd.vh", u8_sat(rounding_shift_right(wild_i16x, wild_u16)), Pattern::DeinterleaveOp0},
{"halide.hexagon.trunc_satb_shr_rnd.vh", i8_sat(rounding_shift_right(wild_i16x, wild_u16)), Pattern::DeinterleaveOp0},
{"halide.hexagon.trunc_satub_shr_rnd.vuh", u8_sat(rounding_shift_right(wild_u16x, wild_u16)), Pattern::DeinterleaveOp0 | Pattern::v65orLater},
{"halide.hexagon.trunc_satub_shr_rnd.vuh", u8_sat(rounding_shift_right(wild_u16x, wild_u16)), Pattern::DeinterleaveOp0},
{"halide.hexagon.trunc_satuh_shr_rnd.vw", u16_sat(rounding_shift_right(wild_i32x, wild_u32)), Pattern::DeinterleaveOp0},
{"halide.hexagon.trunc_sath_shr_rnd.vw", i16_sat(rounding_shift_right(wild_i32x, wild_u32)), Pattern::DeinterleaveOp0},
{"halide.hexagon.trunc_satuh_shr_rnd.vuw", u16_sat(rounding_shift_right(wild_u32x, wild_u32)), Pattern::DeinterleaveOp0},
Expand Down Expand Up @@ -2318,7 +2313,7 @@ Stmt optimize_hexagon_shuffles(const Stmt &s, int lut_alignment) {
}

Stmt scatter_gather_generator(Stmt s) {
// Generate vscatter-vgather instruction if target >= v65
// Generate vscatter-vgather instruction
s = substitute_in_all_lets(s);
s = ScatterGatherGenerator().mutate(s);
s = SyncronizationBarriers().mutate(s);
Expand Down
5 changes: 1 addition & 4 deletions src/LLVM_Runtime_Linker.cpp
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Expand Up @@ -1079,10 +1079,7 @@ std::unique_ptr<llvm::Module> get_initial_module_for_target(Target t, llvm::LLVM
if (t.arch == Target::Hexagon) {
modules.push_back(get_initmod_qurt_hvx(c, bits_64, debug));
modules.push_back(get_initmod_hvx_128_ll(c));
if (t.features_any_of({Target::HVX_v65, Target::HVX_v66})) {
modules.push_back(get_initmod_qurt_hvx_vtcm(c, bits_64,
debug));
}
modules.push_back(get_initmod_qurt_hvx_vtcm(c, bits_64, debug));

} else {
modules.push_back(get_initmod_prefetch(c, bits_64, debug));
Expand Down
27 changes: 4 additions & 23 deletions src/Target.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -286,8 +286,6 @@ Target calculate_host_target() {

bool is_using_hexagon(const Target &t) {
return (t.has_feature(Target::HVX) ||
t.has_feature(Target::HVX_v62) ||
t.has_feature(Target::HVX_v65) ||
t.has_feature(Target::HVX_v66) ||
t.has_feature(Target::HexagonDma) ||
t.arch == Target::Hexagon);
Expand All @@ -297,16 +295,10 @@ int get_hvx_lower_bound(const Target &t) {
if (!is_using_hexagon(t)) {
return -1;
}
if (t.has_feature(Target::HVX_v62)) {
return 62;
}
if (t.has_feature(Target::HVX_v65)) {
return 65;
}
if (t.has_feature(Target::HVX_v66)) {
return 66;
}
return 60;
return 65;
}

} // namespace
Expand Down Expand Up @@ -491,8 +483,6 @@ const std::map<std::string, Target::Feature> feature_name_map = {
{"large_buffers", Target::LargeBuffers},
{"hvx", Target::HVX_128},
{"hvx_128", Target::HVX_128},
{"hvx_v62", Target::HVX_v62},
{"hvx_v65", Target::HVX_v65},
{"hvx_v66", Target::HVX_v66},
{"fuzz_float_stores", Target::FuzzFloatStores},
{"soft_float_abi", Target::SoftFloatABI},
Expand Down Expand Up @@ -1248,8 +1238,6 @@ bool Target::get_runtime_compatible_target(const Target &other, Target &result)
CUDACapability75,
CUDACapability80,
CUDACapability86,
HVX_v62,
HVX_v65,
HVX_v66,
VulkanV10,
VulkanV12,
Expand Down Expand Up @@ -1385,12 +1373,6 @@ bool Target::get_runtime_compatible_target(const Target &other, Target &result)

// Same trick as above for CUDA
int hvx_version = std::min((unsigned)hvx_a, (unsigned)hvx_b);
if (hvx_version < 62) {
output.features.reset(HVX_v62);
}
if (hvx_version < 65) {
output.features.reset(HVX_v65);
}
if (hvx_version < 66) {
output.features.reset(HVX_v66);
}
Expand Down Expand Up @@ -1422,10 +1404,9 @@ void target_test() {
{{"x86-64-linux-vulkan", "x86-64-linux", "x86-64-linux-vulkan"}},
{{"x86-64-linux-vulkan-vk_v13", "x86-64-linux-vulkan", "x86-64-linux-vulkan"}},
{{"x86-64-linux-vulkan-vk_v13", "x86-64-linux-vulkan-vk_v10", "x86-64-linux-vulkan-vk_v10"}},
{{"hexagon-32-qurt-hvx_v65", "hexagon-32-qurt-hvx_v62", "hexagon-32-qurt-hvx_v62"}},
{{"hexagon-32-qurt-hvx_v62", "hexagon-32-qurt", "hexagon-32-qurt"}},
{{"hexagon-32-qurt-hvx_v62-hvx", "hexagon-32-qurt", ""}},
{{"hexagon-32-qurt-hvx_v62-hvx", "hexagon-32-qurt-hvx", "hexagon-32-qurt-hvx"}},
{{"hexagon-32-qurt-hvx_v66", "hexagon-32-qurt", "hexagon-32-qurt"}},
{{"hexagon-32-qurt-hvx_v66-hvx", "hexagon-32-qurt", ""}},
{{"hexagon-32-qurt-hvx_v66-hvx", "hexagon-32-qurt-hvx", "hexagon-32-qurt-hvx"}},
};

for (const auto &test : gcd_tests) {
Expand Down
2 changes: 0 additions & 2 deletions src/Target.h
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Original file line number Diff line number Diff line change
Expand Up @@ -119,8 +119,6 @@ struct Target {
HexagonDma = halide_target_feature_hexagon_dma,
HVX_128 = halide_target_feature_hvx_128,
HVX = HVX_128,
HVX_v62 = halide_target_feature_hvx_v62,
HVX_v65 = halide_target_feature_hvx_v65,
HVX_v66 = halide_target_feature_hvx_v66,
FuzzFloatStores = halide_target_feature_fuzz_float_stores,
SoftFloatABI = halide_target_feature_soft_float_abi,
Expand Down
2 changes: 0 additions & 2 deletions src/runtime/HalideRuntime.h
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Expand Up @@ -1352,7 +1352,6 @@ typedef enum halide_target_feature_t {
halide_target_feature_large_buffers, ///< Enable 64-bit buffer indexing to support buffers > 2GB. Ignored if bits != 64.

halide_target_feature_hvx_128, ///< Enable HVX 128 byte mode.
halide_target_feature_hvx_v62, ///< Enable Hexagon v62 architecture.
halide_target_feature_fuzz_float_stores, ///< On every floating point store, set the last bit of the mantissa to zero. Pipelines for which the output is very different with this feature enabled may also produce very different output on different processors.
halide_target_feature_soft_float_abi, ///< Enable soft float ABI. This only enables the soft float ABI calling convention, which does not necessarily use soft floats.
halide_target_feature_msan, ///< Enable hooks for MSAN support.
Expand All @@ -1365,7 +1364,6 @@ typedef enum halide_target_feature_t {
halide_target_feature_trace_stores, ///< Trace all stores done by the pipeline. Equivalent to calling Func::trace_stores on every non-inlined Func.
halide_target_feature_trace_realizations, ///< Trace all realizations done by the pipeline. Equivalent to calling Func::trace_realizations on every non-inlined Func.
halide_target_feature_trace_pipeline, ///< Trace the pipeline.
halide_target_feature_hvx_v65, ///< Enable Hexagon v65 architecture.
halide_target_feature_hvx_v66, ///< Enable Hexagon v66 architecture.
halide_target_feature_cl_half, ///< Enable half support on OpenCL targets
halide_target_feature_strict_float, ///< Turn off all non-IEEE floating-point optimization. Currently applies only to LLVM targets.
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