XCORE.com I2C Master Component

Status:	Feature complete
Maintainer:	Dan Wilkinson (github: djpwilk)

The I2C Component provides the ability to write and read the I2C Compatible Slave devices.

Key Features

module_i2c:

• Works at 100 Kbps and 400 Kbps
• Supports Clock stretching
• Supports Multi master capability.
• Supports Clock synchronization.

module_i2c_simple / module_i2c_single_port:

• Small footprint
• Works at 100 Kbps and 400 Kbps
• Single system-wide I2C bus with XCore acting as the single master.
• SDA and SCL can be on a single wide port (module_i2c_single_port)

module_i2c_master:

• Works at 100 Kbps and 400 Kbps
• Multiple I2C busses
• Supports Clock stretching
• Support for Multi master capability.
• Support for Clock synchronization.

Firmware Overview

The Component is in the form of a function library and can be called in a thread.

Module_i2c is meant to be deprecated, once module_i2c_master is completed, and once the slave part has been moved to module_i2c_slave.

Known Issues

does not support 10 bit addressing does not support CBUS capability. does not support HS-Mode.

Required Modules

• xcommon git@github.com:xmos/xcommon.git

Instructions for Building Project and running the simulation.

The Software Components for I2C are built using XMOS Development Environment (XDE) Version: 10.4.2 (build 1752) or later. The module can be simulated using test bench. Following steps is to followed to run the simulation

1. import the xcommon and xmos_i2c folders into XMOS Development Environment.

1. open run configuration.

1. In Main tab select simulator in Device options.

1. Select simulator Tab.
2. Tick enable tracing.
3. Tick Pads.
4. In Local Tracing options click on ADD button and select stdcore[1] and ports.
5. Select Pins tab.
6. Enable Pin connections
7. Click on Add Button.

1. Select stdcore[1].

1. Connect Port XS1_PORT_1B to XS1_PORT_1F.
2. Connect Port XS1_PORT_1A to XS1_PORT_1E.
3. Connect Port XS1_PORT_1B to XS1_PORT_1D.
4. Connect Port XS1_PORT_1A to XS1_PORT_1C.
5. Connect Port XS1_PORT_1B to XS1_PORT_1G
6. Connect Port XS1_PORT_1A to XS1_PORT_1H.
7. Connect Port XS1_PORT_1F to XS1_PORT_1D
8. Connect Port XS1_PORT_1E to XS1_PORT_1C.
9. Connect Port XS1_PORT_1F to XS1_PORT_1G.
10. Connect Port XS1_PORT_1E to XS1_PORT_1H.
11. Connect Port XS1_PORT_1D to XS1_PORT_1G.
12. Connect Port XS1_PORT_1C to XS1_PORT_1H.

1. Apply the changes and run.

1. In i2c_test_def.h keep MASTER_TX uncommenting for master transmit and slave receive.
2. For Comment MASTER_TX for slave transmit and master receive.
3. For single master and single slave comment MASTER2 and SLAVE2 or comment MASTER1 and SLAVE1.
4. for single slave and two masters select MASTER1 and MASTER2 comment SLAVE1 or SLAVE2.
5. for two slaves and single master select SLAVE1 and SLAVE2 comment MASTER1 or MASTER2.
6. for two master and two slaves select both MASTER1 and MASTER2, and SLAVE1 and SLAVE2.
7. run the simulation. Check for valid data on the console window.

Support

Issues may be submitted via the Issues tab in this github repo. Response to any issues submitted as at the discretion of the maintainer for this line.