logic circuit for GAL22V10, gives error message

[lynchaj]

Hi,
I am working on a logic circuit and plan to program a GAL22V10 with it. However, the circuit is giving me an error message when I go to make a JEDEC file. "Error during creation of hardware configuration. Only VAR or NOT VAR allowed"

The circuit is fairly simple. The AND gate portion when tested by itself works fine. As does the 74139 demultiplexer. Even when combined they work fine and produce a JEDEC as expected. However, when I connect the 7474 JK flip flop circuit, I get the error message. I think the problem is somehow related to the 7474 JK flip flop because when I do "analysis -> create -> circuit" the flip flop portion of the circuit does not appear in what is produced. Also, I get the error message above when trying to create a JEDEC file.

I searched the examples and found some JK flip flop circuits but none had any clues I could find. I suspect the issue is that the output of the 74139 is feeding a clock input of the JK flip flop and somehow confusing the simulator? Maybe? Or something else.

I don't see a way to add clock input or convert the regular output into a clock signal. Any help from the community? Sorry, it's been many years since engineering school.

[lynchaj]

Thank you for any help in answering my questions

[lynchaj]

Hi, for reasons known only to the great circuit board designer in the sky, the above schematic works in Digital and compiles to JEDEC, CUPL, and can produce a complete circuit in analysis. Not sure why that is but I'll take it.

If anyone could shed some light on this, I would appreciate it very much. Thank you, Andrew Lynch

[hneemann]

It is not possible to analyze circuits with asynchronous flipflops or flipflops with asynchronous set/reset.
Only D and JK flipflops can be used for analyzing.

[hneemann]

But I just found out that in this particular case no error message is generated. This is a bug.

[hneemann]

Please use the latest pre release v0.30-3-gf8b800a .

[lynchaj]

HiOK, good to know.  Thank you for the reply and your help Andrew Lynch On Saturday, March 4, 2023 at 01:40:44 AM EST, Helmut Neemann ***@***.***> wrote: It is not possible to analyze circuits with asynchronous flipflops or flipflops with asynchronous set/reset. Only D and JK flipflops can be used for analyzing. — Reply to this email directly, view it on GitHub, or unsubscribe. You are receiving this because you authored the thread.Message ID: ***@***.***>