Skip to content

i2a2/DPSA

Folders and files

NameName
Last commit message
Last commit date

Latest commit

 

History

4 Commits
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

Repository files navigation

Hardware acceleration of DPSA using FPGAs

Repository of published article at Sensors 2024, 24(9), 2724; https://doi.org/10.3390/s24092724

Abstract

The BC501A sensor is a liquid scintillator frequently used in nuclear physics for detecting fast neutrons. This paper describes a hardware implementation of digital pulse shape analysis (DPSA) for real-time analysis. DPSA is an algorithm that extracts the physically relevant parameters from the detected BC501A signals. The hardware solution is implemented in a MicroTCA system that provides the physical, mechanical, electrical, and cooling support for an AMC board (NAMC-ZYNQFMC) with a Xilinx ZYNQ Ultrascale-MP SoC. The Xilinx FPGA programmable logic implements a JESD204B interface to high-speed ADCs. The physical and datalink JESD204B layers are implemented using hardware description language (HDL), while the Xilinx high-level synthesis language (HLS) is used for the transport and application layers. The DPSA algorithm is a JESD204B application layer that includes a FIR filter and a constant fraction discriminator (CFD) function, a baseline calculation function, a peak detection function, and an energy calculation function. This architecture achieves an analysis mean time of less than 100 μs per signal with an FPGA resource utilization of about 50% of its most used resources. This paper presents a high-performance DPSA embedded system that interfaces with a 1 GS/s ADC and performs accurate calculations with relatively low latency.

Hardware Requirements

The system is based on a Micro Telecommunications Computing Architecture (MicroTCA) chassis and uses a NAMC-ZYNQ-FMC Advanced Mezzanine Card (AMC) whose main component is a Xilinx ZYNQ Ultrascale + MP SoC.

Software Requirements

Vitis Integrated Design Enviroment v2021.1.0 (64-bit)

Usage

JESD204B Board Support Package

The JESD204B standard is implemented in the SoC programmable logic (PL) area to interface the digitizer and the DPSA application.

Please, refer to https://github.com/i2a2/namc_zynqup_fmc_bsp/tree/ad_jesd204_2021.1

DPSA

  1. Clone repository:
  git clone git@github.com:i2a2/DPSA.git
  1. Import the project:
  • File => Import => Import projects from Git => Existing local repository => DPSA
  • Import existing Eclipse projects
  • Select all and import
  1. Make sure you have configured the project's Sysroot, Root FS, and Kernel Image options correctly (Please, refer to https://github.com/i2a2/namc_zynqup_fmc_bsp/tree/ad_jesd204_2021.1).

  2. Edit the binary container settings to add the following lines to the V++ configuration:

[connectivity]
sc=krnl_JESD204B_tx_1.outStream:krnl_JESD204B_rx_1.inStream
sc=krnl_JESD204B_rx_1.outStream_ln0:krnl_dpsa_1.ln0
  1. Build Project using Hardware configuration. This step takes about an hour.

  2. The image should be burned into an SD card.

cd <WORKING_DIRECTORY_PATH>/DPSA_system/Hardware/package/sd_card/
sudo dd if=Image of=/dev/<SD_CARD_DEVICE_FILE_DESCRIPTOR>
  1. Boot the NAMC-ZYNQ-FMC card. To store the BC501A liquid scintillator signals file, it is necessary to expand the Root File System. The ROOT_FS_PARTITION is typically represented by the mmcblkXpY designation.
resize-part /dev/<ROOT_FS_PARTITION>

Releases

No releases published

Packages

No packages published