Zevios ICF3-Z Core
Zevios is original CPU of ICF3-Z. It is 8bit CPU which is implemented with a very small number of transistors, and works in areas that cannot be achieved with a 32bit CPU. "16bit divided 8bit" can be executed in 17 cycles. With conditions, "24bit divided 8bit" can be executed in 17 cycles. It has 16-bit compression instruction that is user defined. Its instruction also be used as a function like a virtual machine.
ASIC and FPGA
Board : Arty
FPGA : Xilinx XC7A35TICSG324-1L
tool : Vivado 2019.2
BRAM 1.5 = 1 (Program Memory 4KB) + 0.5 (Data Memory 2KB) + 0 (micro code)
Data Memory include Register and Scratchpad memory.
Unless otherwise noted, everything in this repository is covered by the Apache License, Version 2.0 (see LICENSE for full text).
Copyright (c) 2019-2020 Naoki Hirayama
The ICF3-Z project aims not to use Japanese taxes.
ICF3-Z & Zevios
E-mail : email@example.com