Mixed Signal RISC-V SoC

Table of Contents

1. Introduction-Mixed Signal SoC
   
2. Tools
   
3. RVMyth
   
4. PLL Specs
   
5. Moving Forward
   • RVMyth:TL-Verilog to Verilog
   • Designing avsdpll
   • Verification
   • RTL Integration and Simulation of RVMYTH+PLL
   • FPGA Flow
6. References
7. Acknowledgements

Introduction - Mixed Signal SoC

Mixed signal SoC is a chip which contains both analog and digital blocks. The designers are adding more analog circuitry and increasing their complexities day by day. Not only that, they also contain digital control logic. As the process nodes shrink, the demand for integration grows. A divide and conquer approach is followed, where the analog and digital structures were dealt with separately. Usually, an analog IP (Intellectual Property) is bought as black- box.

Here, the digital block is the RVMyth RISC-V CPU Core and the analog block is a PLL(Phase Locked Loop). This project aims to integrate these two blocks with the PLL serving as a clock multiplier.

RVMYTH Core: https://github.com/infini8-13/riscv-tlv-core
PLL: https://github.com/vsdip/rvmyth_avsdpll_interface

Tools

Makerchip: Makerchip is a free web-based IDE as well as available as makerchip-app.

Icarus Verilog: Icarus Verilog is an open-source Verilog compiler used for simulation and synthesis.

GTKWave: GTKWave is a fully featured GTK+ based wave viewer, also open-source.

Xilinx Vivado: Xilinx Vivado delivers a SoC-strength, IP-centric and system-centric, next generation development. This project is developed using Vivado ML Edition 2021.1.

SandPiper: Sandpiper is a code generator that generates readable, well-structured, Verilog or SystemVerilog code from the given TL-Verilog code.

RVMyth

5 Stage Pipeline RISC-V32I Core written in Transaction Level Verilog(Later converted to Verilog for SoC Integration)

PLL

Phase Locked Loop IP - avsdpll_1x8 - used a multiplier in this SoC and forms the analog block

Moving Forward

To achieve the integration, a verilog block for the PLL should be generated and the output of the PLL is given as an input to the rvmyth. This will create the interface.

RVMyth: TL-Verilog to Verilog

Using Sandpiper to produce Verilog code from TL-V

1. git clone https://github.com/shivanishah269/vsdfpga.git
2. cd vsdfpga/verilog
3. sandpiper-saas -i rvmyth.tlv -o rvmyth.v --iArgs

Designing avsdpll

Design a PLL as a clock multiplier using verilog and test the functionality.(PLL IP)

1. iverilog avsd_pll_1v8.v pll_tb.v
2. ./a.out
3. gtkwave test.vcd

Verification

• RTL Integration and Simulation of RVMYTH+PLL

  Now integrate both rvmyth and avsdpll using a top level testbench and test it to verify.

  1. iverilog rvmyth_pll_tb.v rvmyth_pll.v clk_gate.v
  2. ./a.out
  3. gtkwave rvmyth_pll.vcd Waveform Output

  Output Waveform in Analog-Depicting the test program

• FPGA Flow

  This flow involves RTL simulation(similar to above) in Vivado, beginning with IP Generation for the PLL and waveform interface as Clocking Wizard and Integrated Logic Analyser(ILA) IPs, respectively. Clocking Wizard generates HDL source code to configure a clock circuit to according our requirements specified in the source code, in our case a PLL acting as a clock multiplier. Next in the pipeline comes synthesis and implementation for the target Zedboard. Implementation involves optimization, placing and routing. It also involves checking of timing constraints.

  

  

  

  

  

  

References

1. https://github.com/infini8-13/riscv-tlv-core
2. https://github.com/vsdip/rvmyth_avsdpll_interface
3. https://github.com/shivanishah269/vsdfpga
4. https://github.com/vsdip/vsdmixedsignalflow

Acknowledgements

• Shivani Shah, IIIT Bangalore.
• Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd.
• Steve Hoover, Founder, Redwood EDA