[Driver][SYCL] Update archive creation with -fsycl-link for FPGA #7325
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When generating archives using -fsycl-link=early|image, any associated generated objects and device binaries are added to the archive for later processing. Archives can also be used in this manner, but creating the archives with 'cr' would just add the archive to the final generated archive, which does not allow the final archive to be used for host linking. Update the archive generation by using 'cqL' for llvm-ar, as that allows for any archives that are pulled in to be added via the contents instead of the archives themselves.
hchilama
approved these changes
Nov 9, 2022
|
Unexpected pass in regression/tanh_fix_test.cpp and failure in Regression/device_num.cpp are known issues. |
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When generating archives using -fsycl-link=early|image, any associated generated objects and device binaries are added to the archive for later processing. Archives can also be used in this manner, but creating the archives with 'cr' would just add the archive to the final generated archive, which does not allow the final archive to be used for host linking.
Update the archive generation by using 'cqL' for llvm-ar, as that allows for any archives that are pulled in to be added via the contents instead of the archives themselves.