SKL: Release v57 event files

This commit releases SKL v57 events and updates mapfile.csv accordingly.
intel · Jun 12, 2023 · 1c3042c · 1c3042c
1 parent f5f47dc
commit 1c3042c
Show file tree

Hide file tree

Showing 5 changed files with 155 additions and 40 deletions.
diff --git a/SKL/events/skylake_core.json b/SKL/events/skylake_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V56",
-    "DatePublished": "04/14/2023",
-    "Version": "56",
+    "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V57",
+    "DatePublished": "06/06/2023",
+    "Version": "57",
     "Legend": ""
   },
   "Events": [
@@ -2403,8 +2403,8 @@
       "EventCode": "0x79",
       "UMask": "0x18",
       "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
-      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
-      "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.",
+      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.DSB_CYCLES_OK]",
+      "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_OK]",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -2426,8 +2426,54 @@
       "EventCode": "0x79",
       "UMask": "0x18",
       "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
-      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
-      "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ.",
+      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]",
+      "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.DSB_CYCLES_ANY]",
+      "Counter": "0,1,2,3",
+      "CounterHTOff": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0",
+      "MSRValue": "0",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "AnyThread": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0"
+    },
+    {
+      "EventCode": "0x79",
+      "UMask": "0x18",
+      "EventName": "IDQ.DSB_CYCLES_OK",
+      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
+      "PublicDescription": "Counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]",
+      "Counter": "0,1,2,3",
+      "CounterHTOff": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0",
+      "MSRValue": "0",
+      "TakenAlone": "0",
+      "CounterMask": "4",
+      "Invert": "0",
+      "AnyThread": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0"
+    },
+    {
+      "EventCode": "0x79",
+      "UMask": "0x18",
+      "EventName": "IDQ.DSB_CYCLES_ANY",
+      "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]",
+      "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Count includes uops that may 'bypass' the IDQ. [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -2656,8 +2702,31 @@
       "EventCode": "0x83",
       "UMask": "0x04",
       "EventName": "ICACHE_64B.IFTAG_STALL",
-      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
-      "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
+      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
+      "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
+      "Counter": "0,1,2,3",
+      "CounterHTOff": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "200003",
+      "MSRIndex": "0",
+      "MSRValue": "0",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "AnyThread": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0"
+    },
+    {
+      "EventCode": "0x83",
+      "UMask": "0x04",
+      "EventName": "ICACHE_TAG.STALLS",
+      "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
+      "PublicDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "200003",
@@ -2863,8 +2932,31 @@
       "EventCode": "0x87",
       "UMask": "0x01",
       "EventName": "ILD_STALL.LCP",
-      "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
-      "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
+      "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]",
+      "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to DECODE.LCP]",
+      "Counter": "0,1,2,3",
+      "CounterHTOff": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0",
+      "MSRValue": "0",
+      "TakenAlone": "0",
+      "CounterMask": "0",
+      "Invert": "0",
+      "AnyThread": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0"
+    },
+    {
+      "EventCode": "0x87",
+      "UMask": "0x01",
+      "EventName": "DECODE.LCP",
+      "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]",
+      "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",
@@ -3691,8 +3783,31 @@
       "EventCode": "0xA8",
       "UMask": "0x01",
       "EventName": "LSD.CYCLES_4_UOPS",
-      "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
-      "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector).",
+      "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_OK]",
+      "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_OK]",
+      "Counter": "0,1,2,3",
+      "CounterHTOff": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "2000003",
+      "MSRIndex": "0",
+      "MSRValue": "0x00",
+      "TakenAlone": "0",
+      "CounterMask": "4",
+      "Invert": "0",
+      "AnyThread": "0",
+      "EdgeDetect": "0",
+      "PEBS": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offcore": "0",
+      "Deprecated": "0"
+    },
+    {
+      "EventCode": "0xA8",
+      "UMask": "0x01",
+      "EventName": "LSD.CYCLES_OK",
+      "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn't come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS]",
+      "PublicDescription": "Counts the cycles when 4 uops are delivered by the LSD (Loop-stream detector). [This event is alias to LSD.CYCLES_4_UOPS]",
       "Counter": "0,1,2,3",
       "CounterHTOff": "0,1,2,3,4,5,6,7",
       "SampleAfterValue": "2000003",

diff --git a/SKL/events/skylake_fp_arith_inst.json b/SKL/events/skylake_fp_arith_inst.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V56",
-    "DatePublished": "04/14/2023",
-    "Version": "56",
+    "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V57",
+    "DatePublished": "06/06/2023",
+    "Version": "57",
     "Legend": ""
   },
   "Events": [

diff --git a/SKL/events/skylake_matrix_bit_definitions.json b/SKL/events/skylake_matrix_bit_definitions.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V56",
-    "DatePublished": "04/14/2023",
-    "Version": "56",
+    "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V57",
+    "DatePublished": "06/06/2023",
+    "Version": "57",
     "Legend": ""
   },
   "Events": [

diff --git a/SKL/events/skylake_uncore.json b/SKL/events/skylake_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2023 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V56",
-    "DatePublished": "04/14/2023",
-    "Version": "56",
+    "Info": "Performance Monitoring Events for 6th Generation Intel(R) Core(TM) Processor - V57",
+    "DatePublished": "06/06/2023",
+    "Version": "57",
     "Legend": ""
   },
   "Events": [

diff --git a/mapfile.csv b/mapfile.csv
@@ -62,24 +62,24 @@ GenuineIntel-6-4F,V21,/BDX/events/broadwellx_matrix.json,offcore,,,
 GenuineIntel-6-4F,V21,/BDX/events/broadwellx_uncore.json,uncore,,,
 GenuineIntel-6-56,V10,/BDW-DE/events/broadwellde_core.json,core,,,
 GenuineIntel-6-56,V10,/BDW-DE/events/broadwellde_uncore.json,uncore,,,
-GenuineIntel-6-4E,V56,/SKL/events/skylake_core.json,core,,,
-GenuineIntel-6-5E,V56,/SKL/events/skylake_core.json,core,,,
-GenuineIntel-6-4E,V56,/SKL/events/skylake_uncore.json,uncore,,,
-GenuineIntel-6-5E,V56,/SKL/events/skylake_uncore.json,uncore,,,
-GenuineIntel-6-4E,V56,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
-GenuineIntel-6-5E,V56,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
-GenuineIntel-6-8E,V56,/SKL/events/skylake_core.json,core,,,
-GenuineIntel-6-9E,V56,/SKL/events/skylake_core.json,core,,,
-GenuineIntel-6-8E,V56,/SKL/events/skylake_uncore.json,uncore,,,
-GenuineIntel-6-9E,V56,/SKL/events/skylake_uncore.json,uncore,,,
-GenuineIntel-6-8E,V56,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
-GenuineIntel-6-9E,V56,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
-GenuineIntel-6-A5,V56,/SKL/events/skylake_core.json,core,,,
-GenuineIntel-6-A6,V56,/SKL/events/skylake_core.json,core,,,
-GenuineIntel-6-A5,V56,/SKL/events/skylake_uncore.json,uncore,,,
-GenuineIntel-6-A6,V56,/SKL/events/skylake_uncore.json,uncore,,,
-GenuineIntel-6-A5,V56,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
-GenuineIntel-6-A6,V56,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
+GenuineIntel-6-4E,V57,/SKL/events/skylake_core.json,core,,,
+GenuineIntel-6-5E,V57,/SKL/events/skylake_core.json,core,,,
+GenuineIntel-6-4E,V57,/SKL/events/skylake_uncore.json,uncore,,,
+GenuineIntel-6-5E,V57,/SKL/events/skylake_uncore.json,uncore,,,
+GenuineIntel-6-4E,V57,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
+GenuineIntel-6-5E,V57,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
+GenuineIntel-6-8E,V57,/SKL/events/skylake_core.json,core,,,
+GenuineIntel-6-9E,V57,/SKL/events/skylake_core.json,core,,,
+GenuineIntel-6-8E,V57,/SKL/events/skylake_uncore.json,uncore,,,
+GenuineIntel-6-9E,V57,/SKL/events/skylake_uncore.json,uncore,,,
+GenuineIntel-6-8E,V57,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
+GenuineIntel-6-9E,V57,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
+GenuineIntel-6-A5,V57,/SKL/events/skylake_core.json,core,,,
+GenuineIntel-6-A6,V57,/SKL/events/skylake_core.json,core,,,
+GenuineIntel-6-A5,V57,/SKL/events/skylake_uncore.json,uncore,,,
+GenuineIntel-6-A6,V57,/SKL/events/skylake_uncore.json,uncore,,,
+GenuineIntel-6-A5,V57,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
+GenuineIntel-6-A6,V57,/SKL/events/skylake_fp_arith_inst.json,fp_arith_inst,,,
 GenuineIntel-6-57,V10,/KNL/events/KnightsLanding_core.json,core,,,
 GenuineIntel-6-57,V10,/KNL/events/KnightsLanding_matrix.json,offcore,,,
 GenuineIntel-6-57,V10,/KNL/events/KnightsLanding_uncore.json,uncore,,,