Fixes: 157 #203
Merged
Fixes: 157 #203
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… replication operator
… a replication operator in output verilog expression
mkorbel1
requested changes
Nov 21, 2022
This was referenced Dec 15, 2022
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Description & Motivation
At present, signExtend uses Mux which generates a SystemVerilog which is not as elegant as the replication operator. This fix removes the use of Mux and introduces another component that generates a replication operator in the output SystemVerilog. Also, when the input signal has a width of 1, the output does not need to be swizzled.
Related Issue(s)
Fixes: 157
Testing
In addition to the existing signExtend tests, added:
Backwards-compatibility
No, this is not a breaking change.
Documentation
No.