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Issue #336: Added power functionality #356
Issue #336: Added power functionality #356
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Looks very good, thank you for the contribution! A few suggestions
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Looking good! Just a couple minor things
Hi @mkorbel1 There is a test case where E.g., Can you please confirm if this is an issue or I misunderstood something. If it's an issue, we need to handle |
@Sanchit-kumar, yes this looks like a bug, thanks for raising it! I think this is a manifestation of #299 which is WIP being addressed in PR #319 (which has been WIP for a while, should probably poke on that). Your test case that reproduces the issue is pretty simple, so I'll make a note on that issue to suggest using that as an additional test case. Sorry you ran into this! |
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Changes look good! A few more things
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Looks great, thank you for the contribution!
Description & Motivation
In SystemVerilog, power (a**b) is a useful function.
It would be nice to have a synthesizable Module and associated functions for generating hardware and SystemVerilog with powers as per issue #336
Testing
Added necessary test cases to test/logic_value_test.dart and test/math_test.dart
Documentation
Yes. Updated both README.md and doc/tutorials/chapter_2/00_basic_logic.md