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Fix bug where generated SV has lint issues with plus and shift-left due to SV width expansion #423

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merged 2 commits into from
Oct 12, 2023

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mkorbel1
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Description & Motivation

Some operations (+, <<) can cause the output of the operation to be larger than the inputs. In ROHD, the output width equals the input width (strictly). The generated SV properly did truncation, but in a way that could flag lint errors due to signal width mismatches.

This change makes it so that we explicitly slice the relevant range rather than rely on SV behavior for signal width mismatch, thus removing lint issues.

Related Issue(s)

Fix #298

Testing

Added a new test that ensures + and << use a slice operation. Don't have an open-source lint tool available for the test suite, but will test it separately to ensure that the fix works properly.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No

@mkorbel1 mkorbel1 merged commit c70a1e5 into intel:main Oct 12, 2023
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@mkorbel1 mkorbel1 deleted the svexpansionfix branch October 12, 2023 22:40
mjayasim9 pushed a commit to mjayasim9/rohd that referenced this pull request Dec 1, 2023
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Successfully merging this pull request may close these issues.

Left-shift can cause width mismatch in generated SystemVerilog
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