verilog2tex: there should be //IO pragma for interface signals

[jjts]

otherwise, IOs in internal modules will inadvertently appear in the doc

another advantage of having this new pragma is that verilog2tex will work regardless if the user chooses to use the lib IO macros or not

if you decide to implement test in i2s please

[P-Miranda]

suggested change example:
update top level port declaration from:

    //START_IO_TABLE axis_in
    `IOB_INPUT(audio_in_s_axis_tvalid, 1), //Audio input stream valid signal.
    `IOB_INPUT(audio_in_s_axis_tdata, 32),  //Audio input stream data signal.
    `IOB_OUTPUT(audio_in_s_axis_tready, 1),  //Audio input stream ready signal.

to:

    //START_IO_TABLE axis_in
    `IOB_INPUT(audio_in_s_axis_tvalid, 1), // V2TEX_IO Audio input stream valid signal.
    `IOB_INPUT(audio_in_s_axis_tdata, 32),  // V2TEX_IO Audio input stream data signal.
    `IOB_OUTPUT(audio_in_s_axis_tready, 1),  // V2TEX_IO Audio input stream ready signal.

update verilog2tex.py to search for // V2TEX_IO lines instead of IOB_INPUT/IOB_OUTPUT
NOTE: also need to update included port headers (example: axi4_m_ports.vh, iob_gen_if.vh)

• generate all included headers via script

• add a flag --top or similar to signal that ports should have the // V2TEX_IO pragma

• A better solution would be to generate ports directly into the top_level.v, starting from a .vt verilog template.

[jjts]

This will be solved by upgrading axi_gen.py to if_gen.py to be able to handle axi, iob and clk/rst interfaces

if_gen.py can later be used by another script that inserts the verilog code into verilog templates instead of generating .vh files that need to be included.

[jjts]

The intent is to have v2tex work even if INPUT or OUTPUT macros are not present