This repository contains a set of Verilog macros to simplify the development of IP cores.
It is used as a submodule in the IOb-SoC (https://github.com/IObundle/iob-soc) RISC-V-based SoC, and associated projects.
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Verilog Modules and Python Scripts for Creating IP Core Build Directories
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IObundle/iob-lib
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Verilog Modules and Python Scripts for Creating IP Core Build Directories
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