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Support extension op sets in the VM compiler and runtime for i64/f32/f64 #2574
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…efs. This makes it easier to read and could be auto generated at some point. Progress on #2574.
Update: progress happening here: https://github.com/google/iree/tree/benvanik-vm64-i64 Most of the ops are now present on both the compiler and runtime sides. Major work remaining is making register allocation aware of 64-bit registers (which to start may just be appended to i32 registers instead of aliasing) and adding the compiler flags/verification for the i64 extension (and others). |
Update; i64 PR out; std->vm is not implemented and I'll file an issue for that specifically, but after a follow-on CL that adds a compiler flag for enabling 64-bit support in the VM this should be completed at this level. Thankfully it's 95% of the work required to support i64, so future work on lowering into the 64-bit VM should be much easier for others to implement. |
The idea is to mimic RISCV and allow extensions to the VM. Some examples are 64-bit integer support, floating point (both 32 and 64-bit), and fixed or variable-length vector ops. These can be implemented as prefix bytes in the primary 0-255 set so we can easily detect and conditionally support ops at runtime (similar to classic cpuid checks).
Major tasks:
Open design issue:
we need to know way up at the flow dialect what our supported types are for both host and device - or support synthesizing appropriate conversions (which can be complicated if multiple devices are involved). For now we can punt on this as we don't support mixed devices, and we can just assert that the VM target supports the same types as the HAL backend for tensors.
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