Skip to content
View jakefreeman's full-sized avatar

Block or report jakefreeman

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. Capstone Capstone Public

    Balancing Robot Senior Project

    VHDL 4 1

  2. Bluefruit-FPGA Bluefruit-FPGA Public

    VHDL module for interfacing Adafruit's Bluefruit LE UART friend with an FPGA

    VHDL

  3. Open-Source-FPGA-Bitcoin-Miner Open-Source-FPGA-Bitcoin-Miner Public

    Forked from fpgaminer/Open-Source-FPGA-Bitcoin-Miner

    A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the fut…

    VHDL

  4. AD7476A_fpga_intf AD7476A_fpga_intf Public

    Systemverilog implementation of a receiver for receiving data from an AD7476A ADC chip,

    SystemVerilog