vsd_workshop - Advanced Physical design

Introduction to OpenLANE - Sky130nm PDK
The main goal is to produce a clean GDSII without human intervention.

Package(QFN-48) --> Chip (Die, Core, Pads)

PLL, SRAM, ADC, DAC - Foundry IP's
RISCV SoC, SPI - Macros
For Digital ASIC opensource design --> RTL design, EDA tools, PDK are the required components.

Docker

Design Preparation

$ docker $ ./flow.tcl -interactive $ package require openlane 0.9 $ prep -design picorv32a

$ run_synthesis

Floorplanning

1. It defines the width and height of core and die (dimensions of chip)
2. Also, define the locations of preplaced cells. Parameters - Utilization factor and Aspect ratio

$ run_floorplan

PDN generation was successful

$ picorv32a.floorplan def file

Placement

$ run_placement

$ picorv32a.placement def file

$ git clone nickson jose - vsdstdcelldesign

$ Sky130_inv.spice

ngspice

$ ngspice sky130_inv.spice $ plot y vs time a

$ grid 0.46um 0.34um 0.23um 0.17um

STA

Clock Tree Synthesis (CTS)

$ run_cts

Routing

$ run_routing