[SX127x] When clearing the FHSS interrupt, don't also clear all the others #1155
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Writing
1
bits to the ReqIrqFlags register clears the corresponding interrupt sources.Before this commit, the
clearFHSSInterrupt()
function would clear all set bits, plus unconditionally clear theFhssChangeChannel
bit. This could cause the following problem:FhssChangeChannel
interrupt. Each interrupt clears all other interrupt bits.FhssChangeChannel
to request a hop back to the starting channel, and also setsRxDone
to indicate that there is a complete packet to read from the FIFO. If the packet had CRC enabled and the CRC failed, thePayloadCrcError
bit will also be set at this point.FhssChangeChannel
interrupt before theRxDone
interrupt, the other two bits (RxDone
andPayloadCrcError
) will be lost. At worst this will mean that the packet will not be read (but will remain in the FIFO). At best this will mean thatreadData()
will not know that the packet failed CRC, and will deliver a corrupted packet.The old behavior seems like a just a simple bug, if i've missed something here please let me know.