What a brilliant resource #1
Comments
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Large number of tiny Forth CPU's are of interest to me
The three that impress me the most:
https://sourceforge.net/projects/mecrisp/files/ based on the J1 with
versions for 16, 32 and 64-bit register size
https://github.com/microCore-VHDL/microCore also has indexing into the
stack
any of the Forth machines with 5-bit instructions classic Forth engine
As for RISC-V with modest LUT counts:
https://github.com/gsmecher/minimax micro-coded
https://github.com/stnolting/neorv32 LUT counts for
various configurations
RISC with small floating-point and compiler
http://www.astrobe.com/RISC5/ by none other
than Niklaus Wirth
I've considered applying for a grant to do roughly what you are saying:
Have the students implement and study several open-source CPU designs,
preferably including accumulator, RISC and stack machines. Then do one of
their design.
I'll add some more text to my github webpage..
There are a couple of web pages that list the more established designs.
https://en.wikipedia.org/wiki/Soft_microprocessor
http://1-core.com/library/digital/soft-cpu-cores/
Jim Brakefield
…On Mon, Apr 3, 2023 at 2:19 PM PythonLinks ***@***.***> wrote:
Thank you so much for creating this.
I am a long time software developer, who just started a master's degree in
EE Digital design a month ago. Large number of tiny Forth CPU's are of
interest to me, but the reality is that maybe they do not do any better for
the space consumed, than a bigger CPU.
So two comments. A more detailed page on how people could help you would
be more interesting. And a specific example would be more interesting. In
my case the J1 as a stack processor, versus some RISC-V chip is what I
would be interested in analyzing.
No promises that I will do it. I am just a curious person, a bit lost, and
exploring. On the other hand a detailed benchmark comparing just the two
chips would indeed be most interesting. Also Ting's EP24 is of maybe even
greater interest to me.
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Thank you so much. With 500 known softcore cpus, it is essential to have someone like you curate them and recommend the best ones. The microcore one looks particularly interesting. They have the right idea. To make FPGA development more accessible. It references the Transputer Pause instruction, and allows for multiple data areas to hold multiple stacks. Perfect, just what I need, but was not smart enough to ask for, or even think possible. I want to call my project the Forth transputer, so when he referenced ideas from the transputer, I was hooked. More seriously he has very needed functionality.
You did not give a specific link, but I am considering Ting's work. Sadly now deceased. He optimized both the eforth and the cpus to work together. And he has a 24 bit version, perfect for vision. And I also have a preference for VHDL over Verilog. "Explicit is better than implicit" is part of the Zen of Python. Ting wrote a book on Zen and Forth. The J1, is very popular, there must be a reason for that. I need to understand it. Good to know the best version is the mecrisp. And of course I need to pay attention to the Risc V chips. Good to know which ones to look at. One thought. It would be nice if it were a database, so I could decide how to sort and filter them. So thanks again, please keep up this very useful service. |
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would be nice if it were a database, so I could decide how to sort and
filter them
Added the "base" spreadsheet (onesheet_up_cores_230405.xlsx), sorted by
design name. Let me know if you need any of the other sheets.
At one time one could cut and paste from the PDF files into a spreadsheet.
Does not appear to work currently (pastes into a single column).
Jim Brakefield
…On Wed, Apr 5, 2023 at 12:44 PM PythonLinks ***@***.***> wrote:
Thank you so much. With 500 known softcore cpus, it is essential to have
someone like you curate them and recommend the best ones.
The microcore one looks particularly interesting. They have the right
idea. To make FPGA development more accessible.
It references the Transputer Pause instruction, and allows for multiple
data areas to hold multiple stacks. Perfect, just what I need, but was not
smart enough to ask for, or even think possible.
I want to call my project the Forth transputer, so when he referenced
ideas from the transputer, I was hooked. More seriously he has very needed
functionality.
any of the Forth machines with 5-bit instructions classic Forth engine.
You did not give a specific link, but I am considering Ting's work. Sadly
now deceased. He optimized both the eforth and the cpus to work together.
And he has a 24 bit version, perfect for vision.
And I also have a preference for VHDL over Verilog. "Explicit is better
than implicit" is part of the Zen of Python. Ting wrote a book on Zen and
Forth.
The J1, is very popular, there must be a reason for that. I need to
understand it. Good to know the best version is the mecrisp.
And of course I need to pay attention to the Risc V chips. Good to know
which ones to look at.
One thought. It would be nice if it were a database, so I could decide how
to sort and filter them.
So thanks again, please keep up this very useful service.
—
Reply to this email directly, view it on GitHub
<#1 (comment)>,
or unsubscribe
<https://github.com/notifications/unsubscribe-auth/AJ7RCBCL6B74D6BLWVSQMFLW7WVPNANCNFSM6AAAAAAWRXQKUQ>
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Thank you. |
Thank you so much for creating this.
I am a long time software developer, who just started a master's degree in EE Digital design a month ago. Large number of tiny Forth CPU's are of interest to me, but the reality is that maybe they do not do any better for the space consumed, than a bigger CPU.
So two comments. A more detailed page on how people could help you would be more interesting. And a specific example would be more interesting. In my case the J1 as a stack processor, versus some RISC-V chip is what I would be interested in analyzing.
No promises that I will do it. I am just a curious person, a bit lost, and exploring. On the other hand a detailed benchmark comparing just the two chips would indeed be most interesting. Also Ting's EP24 is of maybe even greater interest to me.
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