MAPD A: FPGA VHDL Project in Vivaldo

Project: Bubble Sort Algorithm and the UART transmitter/reciver

• Project Report
• PC Juptyer Notebook
• Project Files

Hardware Setup: ARTY A7 FPGA

Our board:
xc7a35tcsg324-1

Constraint master file:
https://github.com/Digilent/digilent-xdc/blob/master/Arty-A7-35-Master.xdc

Pin Maps and board info:
https://digilent.com/reference/programmable-logic/arty-a7/reference-manual