GitHub - jqtangust/3_Stage_MIPS_CPU: 2020西北工业大学计算机学院计算机组成原理与系统结构试点班 Computer Architecture Principle and System Structure pilot class, School of Computer science, Northwestern Polytechnical University

3_Stage_MIPS_CPU

Open source repository to build a Simple three - stage pipeline CPU, based on MIPS instruction system

西北工业大学组成原理试点班，同时也是体系结构比赛代码

完成了全部测试点和上板调试

PDF为设计图

欢迎学弟学妹参考和star，不要抄袭

Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
3_stage.pdf		3_stage.pdf
ADD.v		ADD.v
ALU.v		ALU.v
Branch.v		Branch.v
CP0.v		CP0.v
ControlHAZARD.v		ControlHAZARD.v
Decode.v		Decode.v
ECP.v		ECP.v
EXE.v		EXE.v
Forward.v		Forward.v
LICENSE		LICENSE
README.md		README.md
addr_load.v		addr_load.v
addr_store.v		addr_store.v