💻
FPGA Enthusiast
BS/MS Worcester Polytechnic Insititute
- Long Island, NY
- https://www.linkedin.com/in/jrl2000/
Block or Report
Block or report jrl-2000
Report abuse
Contact GitHub support about this user’s behavior. Learn more about reporting abuse.
Report abusePinned Loading
-
RISC-V-Single-Cycle-CPU
RISC-V-Single-Cycle-CPU Public archive50MHz RISC-V Single-Cycle CPU in Verilog; Xilinx AMD Vivado 2020.2
Verilog
-
SSC-Algorithm-BIST-Design
SSC-Algorithm-BIST-Design Public archiveRandom Test Socket (RTS) Built-In-Self-Test for the Sort Selection Algorithm and Adding CPU
Verilog 1
-
-
Keyboard-Firmware
Keyboard-Firmware PublicTofu65 KBDFans 67 Key Keyboard Firmware and 5 key Macro Pad Firmware
-
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.