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283 contributions in the last year

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Contribution activity

January 2022

Opened 1 pull request in 1 repository
riscv/riscv-profiles 1 merged

Created an issue in riscv/riscv-profiles that received 5 comments

Relax stvec.base requirement for RVA20S64

Can we relax the RVA20S64 stvec.base alignment requirement to >=4 bytes? E.g., >=64 bytes? I can't see a reason that app processor would need that …

Opened 1 other issue in 1 repository
riscv/riscv-fast-interrupt 1 open

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