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250 contributions in the last year

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Contribution activity

November 2019

Created an issue in riscv/riscv-v-spec that received 1 comment

Sign or zero extend AMO addresses when SEW<XLEN

Current PoR for AMO addresses does sign-extension of elements when SEW<XLEN. We recently changed indexed load/stores to have zero-extension of offs…

1 comment

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