Modify NB voltage AMD fam12h #3
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Hi @vinibali sorry for the late reply. It is possible to do the NB voltages, the reason I left it out is because the implementation is quite different between the various families of AMD CPU's, although I can create a branch just for the 12h family for North Bridge voltages, I might do that in the next few weeks. |
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Hi @kevinlekiller. |
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Hi @vinibali, I'm currently looking at the BIOS/Kernel dev guide for 12h. If you look at the PDF: http://support.amd.com/TechDocs/41131.pdf on page 469, there is no mention of a writable field for NbVid, although if you look at the 10h manual for example http://support.amd.com/TechDocs/31116.pdf on page 429, there is a writable field for NbVid at bits 31:25. I've just looked at most of the guides from 10h to 16h and only 10h mentions that writable NbVid field at 31:25. It could be they forgot to include the information in those other CPU families. Do you know if FusionTweaker has the source code published? We could check which bits it's working on and confirm if it's 31:25 like in 10h. |
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I found the FusionTweaker source code, I looked over it quickly, it's a large project so it's hard to to follow, but I think it's falling back on 10h numbers if the CPU is not a 16h : https://github.com/Jeje2312/fusiontweaker/blob/master/FusionTweaker/PStateMsr.cs#L246 |
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I've fount the code.google variant too. |
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I'm looking at the amdctl code, it seems I've already implemented changing the voltage for the north bridge (-n Set north bridge voltage id (vid).), I can't see any code blocking 12h CPU's from doing it also. Did you mean the north bridge fid / did maybe? I think the issue with those is how much it varies between the CPU families. |
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Yes, the amdctl was able to show some value from the NBvid. So the program was able to print some data in the past too, but seems like the value is false. I was not enought brave to execute any command to change the NBvid. |
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Yeah that seems off, 12h CPU's might have a different way to calculate the voltage, I'll investigate, thanks! |
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I've done some tests on a 15h someone gave me access to which is similar to 12h, in that the registers for the individual Pstates (0xc0010064 and up) have no NB vid field and trying to use the same field bits from the "current" Pstate results in getting no data (hence the 0 and 1550uV). I figured, what if I try changing the current Pstate and getting the NB vid from the current Pstate. That did not work because when I change the current Pstate, it changes back instantly (because of AMD Cool n Quiet) and I have no time to get or set the data for the intended Pstate, and trying to force that Pstate by setting the min/max Pstate is not possible since those fields are read only (page 468 in 12h guide). I'm not sure what the other tools are doing to set the voltage for individual Pstates, I went through fusiontweaker's source code a few times but it's very hard to follow. My guess is they found the right bits to set, which are undocumented in the AMD kernel and bios dev guides. I found another tool called k15ctl https://github.com/tud-zih-energy/k15ctl which I tried on the 15h CPU I have access to, but it also shows 0 and 1.55v for the NB, so I assume he made the same mistake I did. The mistake was, when I was going through the guides months ago, I assumed the NbVid field was missing from the individual Pstates (MSRC001_00[6B:64]) because I thought the person who wrote it forgot to put it in the guide, since the field is in the COFVID Status Register. For now I will disable the -n switch for non 10h CPU's, as I don't have a Windows AMD computer I can't compile / debug fusiontweaker to see what exactly it's doing (which bits it's trying to set, maybe someone else can figure that out for us and submit a PR in the future?). |
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I've done a few test. Program Version : AIDA64 v5.70.3800 ------[ CPU Info ]------ CPU Type : QuadCore AMD A8-3820, 2500 MHz (25 x 100) Tjmax Temperature : 0 Celsius ------[ Logical CPU #0 ]------ allcpu: Package 0 / Core 0 / Thread 0: Valid CPUID 00000000: 00000006-68747541-444D4163-69746E65 [AuthenticAMD] ------[ Logical CPU #1 ]------ allcpu: Package 0 / Core 1 / Thread 0: Valid CPUID 00000000: 00000006-68747541-444D4163-69746E65 [AuthenticAMD] ------[ Logical CPU #2 ]------ allcpu: Package 0 / Core 2 / Thread 0: Valid CPUID 00000000: 00000006-68747541-444D4163-69746E65 [AuthenticAMD] ------[ Logical CPU #3 ]------ allcpu: Package 0 / Core 3 / Thread 0: Valid CPUID 00000000: 00000006-68747541-444D4163-69746E65 [AuthenticAMD] ------[ All CPUs ]------ CPU 0: APICID 0 / Package 0 / Core 0 / Thread 0: Valid ------[ MSR Registers ]------ CPU Clock (Normal): 2500 MHz PerformanceFrequency = 2441416 CPU Clock M.Method = 6 (APIC K10) APIC Clock = 200.00 MHz (AT = 104844 / TT = 15012 / try = 1 / SKL = 0.00 MHz) ##############END Voltages set by Fusiontweaker: Program Version : AIDA64 v5.70.3800 ------[ CPU Info ]------ CPU Type : QuadCore AMD A8-3820, 2800 MHz (28 x 100) Tjmax Temperature : 0 Celsius ------[ Logical CPU #0 ]------ allcpu: Package 0 / Core 0 / Thread 0: Valid CPUID 00000000: 00000006-68747541-444D4163-69746E65 [AuthenticAMD] ------[ Logical CPU #1 ]------ allcpu: Package 0 / Core 1 / Thread 0: Valid CPUID 00000000: 00000006-68747541-444D4163-69746E65 [AuthenticAMD] ------[ Logical CPU #2 ]------ allcpu: Package 0 / Core 2 / Thread 0: Valid CPUID 00000000: 00000006-68747541-444D4163-69746E65 [AuthenticAMD] ------[ Logical CPU #3 ]------ allcpu: Package 0 / Core 3 / Thread 0: Valid CPUID 00000000: 00000006-68747541-444D4163-69746E65 [AuthenticAMD] ------[ All CPUs ]------ CPU 0: APICID 0 / Package 0 / Core 0 / Thread 0: Valid ------[ MSR Registers ]------ CPU Clock (Normal): 2800 MHz PerformanceFrequency = 2441416 CPU Clock M.Method = 6 (APIC K10) APIC Clock = 200.00 MHz (AT = 104830 / TT = 15010 / try = 1 / SKL = 0.00 MHz) Meanwhile I asked the developer Sven Wittek to join, will see :) |
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It looks from those screenshots like the northbridge have their own P-states. These are described on page 318: https://support.amd.com/TechDocs/41131.pdf But they are not model specific registers, according to page 148 these are "PCI-defined configuration space" registers, which I have no experience with. |
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Hi @vinibali, I've been reading more about the PCI space registers, I've been testing on a AMD A10-7870k, I got this so far: Detected CPU model 38h, from family 15h with 4 CPU cores. I'm not sure if that is correct, because I can't find any information on the a10-7870k for northbrige voltage / clock speed, although those numbers seem low to me. I got this information by accessing the data on the filesystem itself, "/sys/devices/pci0000:00/0000:00:18.5/config" D18F5x160 is what the AMD guide says P-state 0 is, D18 is the the PCI device, F5 is the function and x160 is hexadecimal for the address where the data is. I could make a branch to read that data for 12h so we can compare to your logs above, I'll report back when I do that. |
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I've adjusted my math for the clock speed, it seems better, I did find a screenshot of a 7850k which matches at least 1 of the clock speeds: http://cdn.overclock.net/7/71/900x900px-LL-71c07b3e_Beast.jpeg NB Pstate 0: 900uV 1800MHz I think the math for the voltage is different than CPU's, I'll have to dig more. Hopefully I can find more info for the 7850k/7870k/7890k on NB p-states to confirm numbers. |
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So it was indeed a difference in math for the NB voltage on 15h (which is poorly documented). I was able to confirm my numbers using this tool: https://github.com/johkra/amdmsrtweaker-lnx Here's with the updated math: Currently the NB code is just for the 7870k processor I have access to, so I will need to rewrite it to be more modular and support 12h and the other families. Edit: Found an output of amdmsrtweaker for the 7870k: http://cdn.overclock.net/f/fe/900x900px-LL-fe4b4acb_AmdMsrTweaker_4FlagshipApus.png although it's a bit late now. |
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Hi @kevinlekiller. |
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I'm now reading the 12h manual for NB vid's. https://support.amd.com/TechDocs/41131.pdf Reading the vid seems simple, there's 2 addresses for 2 P-states Pstate 0 is at page 318 (D18F3xDC Clock Power/Timing Control 2 Register) Pstate 1 is at page 350 (D18F6x90 NB P-state Config Low) The complex part seems to be writing. It says we need to set D18F6x90[NbPsCtrlDis] to 1, and that says D18F6x90[NbPsLock] needs to be 1 also. Once both those are 1, then the Vid can be changed, then it says we need to wait D18F3xD8[VSRampSlamTime] before resetting D18F6x90[NbPsCtrlDis], which I guess means D18F6x90[NbPsLock] needs to be reset also after. |
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I will work on adding code to read the 12h NB vid's first so we can confirm if they match what you posted in Aida64, then I'll work on the code to set it. |
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I pushed the changes to read the 12h NB p-state vids to a branch, you can download here: https://github.com/kevinlekiller/amdctl/archive/12h_NbVid.zip |
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Sorry for the late reply. |
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Thanks, I will merge that branch and start working on being able set the vid's. |
Hello.
It's a great project. Are you planning to implement a function to modify the Llano APU's NB voltages? In FusionTweaker I can do this, but unfortunately in Linux there is no tool to do that, I'm also using TurionPowerControl at the same time, but the project seems like dead. If you have any idea or some code to test, than I have a desktop and mobile with the 1st gen AMD APU.
Thanks
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