Joglekar LTSpice

Joglekar_Linear_Resistance_Switch/Ltspice/README.md

@@ -4,7 +4,7 @@
 |---|---|---|
 |SPICE Subcircuit|SPICE|LTSpice|
 
-Other names: "The Ideal Memristor", "The nonlinear Dopant Drift", "The Resistance Switch" or "The HP Model"
+Other names: "The Ideal Memristor", "The Resistance Switch" or "The HP Model"
 
 ## Sources
 

Joglekar_Linear_Resistance_Switch/Ltspice2/README.md

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+## About 
+
+| Model Class | Model Language | Simulator |
+|---|---|---|
+|SPICE Subcircuit|SPICE|LTSpice|
+
+Other names: "The Ideal Memristor", "The Resistance Switch"
+
+## Sources
+
+1. Original Source of SPICE Model: <https://cyakopcic1.files.wordpress.com/2014/02/memristor-spice-modeling.pdf>
+
+## How to Run Model
+
+1. LTSpice Intro - [The Joglekar Resistance Switch Memristor Model in LTSpice](http://knowm.org/the-joglekar-resistance-switch-memristor-model-in-ltspice/)
+1. LTSpice - [Memristor Models in LTSpice](http://knowm.org/memristor-models-in-ltspice/)

Joglekar_Linear_Resistance_Switch/Ltspice2/memristor_joglekar2.sub

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+* HP Memristor SPICE Model Using Joglekar Window
+
+* Connections:
+* TE:  Top electrode
+* BE:  Bottom electrode
+* XSV: External connection to plot state variable
+*      that is not used otherwise
+
+.SUBCKT MEM_JOGLEKAR TE BE XSV 
+
+* Ron: Minimum device resistance
+* Roff: Maximum device resistance
+* D:   Width of the thin film
+* uv:  Dopant mobility
+* p:   Parameter for window function
+* x0:   State variable initial value
+
+.params Ron=100 Roff=10K x0=.56 D=12N uv=50F p=7
+
+* Joglekar Window Function
+.func f(V1) = 1-pow((2*V1-1),(2*p))
+
+* Memristor I-V Relationship
+.func IVRel(V1,V2) = V1/(Ron*V2 + Roff*(1-V2))
+
+* Circuit to determine state variable
+Gx 0 XSV value={ I(Gmem)*Ron*uv*f(V(XSV,0))/pow(D,2) }
+Cx XSV 0 {1}
+.ic V(XSV) = x0
+
+* Current source representing memristor
+Gmem TE BE value={IVRel(V(TE,BE),V(XSV,0))}
+
+.ENDS MEM_JOGLEKAR

Joglekar_Linear_Resistance_Switch/Ltspice2/memristor_joglekar2_sim_IV.plt

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+[Transient Analysis]
+{
+   Npanes: 2
+   Active Pane: 1
+   {
+      traces: 1 {336592898,0,"Ix(U1:TE)"}
+      Parametric: "V(n001)"
+      X: (' ',2,-1.2,0.02,1.2)
+      Y[0]: ('m',1,-0.001,0.0002,0.0012)
+      Y[1]: ('_',0,1e+308,0,-1e+308)
+      Amps: ('m',0,0,1,-0.001,0.0002,0.0012)
+      Log: 0 0 0
+      NeyeDiagPeriods: 0
+      TeyeEnd: 3
+   },
+   {
+      traces: 1 {268959747,0,"V(nc_01)"}
+      Parametric: "V(n001)"
+      X: (' ',2,-1.2,0.02,1.2)
+      Y[0]: (' ',2,0.21,0.07,1.05)
+      Y[1]: ('_',0,1e+308,0,-1e+308)
+      Volts: (' ',0,0,2,0.21,0.07,1.05)
+      Log: 0 0 0
+      NeyeDiagPeriods: 0
+      TeyeEnd: 3
+   }
+}

Joglekar_Linear_Resistance_Switch/Ltspice2/memristor_joglekar2_sim_T.plt

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+[Transient Analysis]
+{
+   Npanes: 2
+   Active Pane: 1
+   {
+      traces: 2 {268959747,0,"V(n001)"} {336592898,1,"Ix(U1:TE)"}
+      X: ('m',0,0,0.02,0.2)
+      Y[0]: (' ',1,-1,0.2,1)
+      Y[1]: ('µ',0,-0.00042,7e-05,0.00042)
+      Volts: (' ',0,0,1,-1,0.2,1)
+      Amps: ('µ',0,0,0,-0.00042,7e-05,0.00042)
+      Log: 0 0 0
+      NeyeDiagPeriods: 0
+      TeyeEnd: 3
+   },
+   {
+      traces: 1 {268959748,0,"V(nc_01)"}
+      X: ('m',0,0,0.02,0.2)
+      Y[0]: ('m',0,0.52,0.04,0.96)
+      Y[1]: ('µ',0,1e+308,7e-05,-1e+308)
+      Volts: ('m',0,0,0,0.52,0.04,0.96)
+      Log: 0 0 0
+      NeyeDiagPeriods: 0
+      TeyeEnd: 3
+   }
+}

Joglekar_Linear_Resistance_Switch/Ltspice2/memristor_with_state.asy

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+Version 4
+SymbolType CELL
+LINE Normal 4 33 -4 33
+LINE Normal 0 -48 0 -32
+LINE Normal 0 48 0 33
+LINE Normal 32 0 0 0
+CIRCLE Normal 4 33 -4 0
+CIRCLE Normal 4 -32 -4 0
+SYMATTR Prefix X
+SYMATTR Description Parameterized Memristor
+PIN 0 -48 RIGHT 8
+PINATTR PinName TE
+PINATTR SpiceOrder 1
+PIN 0 48 RIGHT 8
+PINATTR PinName BE
+PINATTR SpiceOrder 2
+PIN 32 0 LEFT 8
+PINATTR PinName xsv
+PINATTR SpiceOrder 3