Address some Verilog lints and weaknesses #94
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The amount of entropy tested by the `@` op-test is pretty low, and I have observed on multiple occasions the test passing even when the hardware is not doing its job. The current commit strengthens the randomization test a bit. An even stronger test might ensure that a sole one or zero in a word of zeros or ones is being extracted successfully.
The purpose of the Bit function, as it was introduced in commit eda7dc4, was to keep columnar alignment for readability. As of commit f98aba7, the contained expression shrank significantly, but could not be inlined directly since its result width was too wide. Now I recognize that I should have been using bit-indexing instead of bit-shifting anyway, and the silly function can be removed entirely. As a happy side-effect, this change addresses a bit-width lint noted by Verilator.
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In the process of introducing Verilator support (#48), I found some minor issues that Verilator rightly complains about. They are collected here.