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KVM: selftests: Return a value from vcpu_get_reg() instead of using an out-param
Return a uint64_t from vcpu_get_reg() instead of having the caller provide a pointer to storage, as none of the vcpu_get_reg() usage in KVM selftests accesses a register larger than 64 bits, and vcpu_set_reg() only accepts a 64-bit value. If a use case comes along that needs to get a register that is larger than 64 bits, then a utility can be added to assert success and take a void pointer, but until then, forcing an out param yields ugly code and prevents feeding the output of vcpu_get_reg() into vcpu_set_reg(). Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Claudio Imbrenda <imbrenda@linux.ibm.com> Link: https://lore.kernel.org/r/20241128005547.4077116-3-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
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-78
lines changed

15 files changed

+78
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lines changed

‎tools/testing/selftests/kvm/aarch64/aarch32_id_regs.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ static void test_user_raz_wi(struct kvm_vcpu *vcpu)
9797
uint64_t reg_id = raz_wi_reg_ids[i];
9898
uint64_t val;
9999

100-
vcpu_get_reg(vcpu, reg_id, &val);
100+
val = vcpu_get_reg(vcpu, reg_id);
101101
TEST_ASSERT_EQ(val, 0);
102102

103103
/*
@@ -106,7 +106,7 @@ static void test_user_raz_wi(struct kvm_vcpu *vcpu)
106106
*/
107107
vcpu_set_reg(vcpu, reg_id, BAD_ID_REG_VAL);
108108

109-
vcpu_get_reg(vcpu, reg_id, &val);
109+
val = vcpu_get_reg(vcpu, reg_id);
110110
TEST_ASSERT_EQ(val, 0);
111111
}
112112
}
@@ -126,14 +126,14 @@ static void test_user_raz_invariant(struct kvm_vcpu *vcpu)
126126
uint64_t reg_id = raz_invariant_reg_ids[i];
127127
uint64_t val;
128128

129-
vcpu_get_reg(vcpu, reg_id, &val);
129+
val = vcpu_get_reg(vcpu, reg_id);
130130
TEST_ASSERT_EQ(val, 0);
131131

132132
r = __vcpu_set_reg(vcpu, reg_id, BAD_ID_REG_VAL);
133133
TEST_ASSERT(r < 0 && errno == EINVAL,
134134
"unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
135135

136-
vcpu_get_reg(vcpu, reg_id, &val);
136+
val = vcpu_get_reg(vcpu, reg_id);
137137
TEST_ASSERT_EQ(val, 0);
138138
}
139139
}
@@ -144,7 +144,7 @@ static bool vcpu_aarch64_only(struct kvm_vcpu *vcpu)
144144
{
145145
uint64_t val, el0;
146146

147-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
147+
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
148148

149149
el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
150150
return el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY;

‎tools/testing/selftests/kvm/aarch64/debug-exceptions.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -501,7 +501,7 @@ void test_single_step_from_userspace(int test_cnt)
501501
TEST_ASSERT(ss_enable, "Unexpected KVM_EXIT_DEBUG");
502502

503503
/* Check if the current pc is expected. */
504-
vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc), &pc);
504+
pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
505505
TEST_ASSERT(!test_pc || pc == test_pc,
506506
"Unexpected pc 0x%lx (expected 0x%lx)",
507507
pc, test_pc);
@@ -583,7 +583,7 @@ int main(int argc, char *argv[])
583583
uint64_t aa64dfr0;
584584

585585
vm = vm_create_with_one_vcpu(&vcpu, guest_code);
586-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &aa64dfr0);
586+
aa64dfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1));
587587
__TEST_REQUIRE(debug_version(aa64dfr0) >= 6,
588588
"Armv8 debug architecture not supported.");
589589
kvm_vm_free(vm);

‎tools/testing/selftests/kvm/aarch64/hypercalls.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,7 @@ static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu)
173173
const struct kvm_fw_reg_info *reg_info = &fw_reg_info[i];
174174

175175
/* First 'read' should be an upper limit of the features supported */
176-
vcpu_get_reg(vcpu, reg_info->reg, &val);
176+
val = vcpu_get_reg(vcpu, reg_info->reg);
177177
TEST_ASSERT(val == FW_REG_ULIMIT_VAL(reg_info->max_feat_bit),
178178
"Expected all the features to be set for reg: 0x%lx; expected: 0x%lx; read: 0x%lx",
179179
reg_info->reg, FW_REG_ULIMIT_VAL(reg_info->max_feat_bit), val);
@@ -184,7 +184,7 @@ static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu)
184184
"Failed to clear all the features of reg: 0x%lx; ret: %d",
185185
reg_info->reg, errno);
186186

187-
vcpu_get_reg(vcpu, reg_info->reg, &val);
187+
val = vcpu_get_reg(vcpu, reg_info->reg);
188188
TEST_ASSERT(val == 0,
189189
"Expected all the features to be cleared for reg: 0x%lx", reg_info->reg);
190190

@@ -214,7 +214,7 @@ static void test_fw_regs_after_vm_start(struct kvm_vcpu *vcpu)
214214
* Before starting the VM, the test clears all the bits.
215215
* Check if that's still the case.
216216
*/
217-
vcpu_get_reg(vcpu, reg_info->reg, &val);
217+
val = vcpu_get_reg(vcpu, reg_info->reg);
218218
TEST_ASSERT(val == 0,
219219
"Expected all the features to be cleared for reg: 0x%lx",
220220
reg_info->reg);

‎tools/testing/selftests/kvm/aarch64/no-vgic-v3.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,7 @@ int main(int argc, char *argv[])
164164
uint64_t pfr0;
165165

166166
vm = vm_create_with_one_vcpu(&vcpu, NULL);
167-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &pfr0);
167+
pfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
168168
__TEST_REQUIRE(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_GIC), pfr0),
169169
"GICv3 not supported.");
170170
kvm_vm_free(vm);

‎tools/testing/selftests/kvm/aarch64/psci_test.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -111,8 +111,8 @@ static void assert_vcpu_reset(struct kvm_vcpu *vcpu)
111111
{
112112
uint64_t obs_pc, obs_x0;
113113

114-
vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc), &obs_pc);
115-
vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.regs[0]), &obs_x0);
114+
obs_pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
115+
obs_x0 = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.regs[0]));
116116

117117
TEST_ASSERT(obs_pc == CPU_ON_ENTRY_ADDR,
118118
"unexpected target cpu pc: %lx (expected: %lx)",
@@ -152,7 +152,7 @@ static void host_test_cpu_on(void)
152152
*/
153153
vcpu_power_off(target);
154154

155-
vcpu_get_reg(target, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), &target_mpidr);
155+
target_mpidr = vcpu_get_reg(target, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1));
156156
vcpu_args_set(source, 1, target_mpidr & MPIDR_HWID_BITMASK);
157157
enter_guest(source);
158158

‎tools/testing/selftests/kvm/aarch64/set_id_regs.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -346,7 +346,7 @@ static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
346346
uint64_t mask = ftr_bits->mask;
347347
uint64_t val, new_val, ftr;
348348

349-
vcpu_get_reg(vcpu, reg, &val);
349+
val = vcpu_get_reg(vcpu, reg);
350350
ftr = (val & mask) >> shift;
351351

352352
ftr = get_safe_value(ftr_bits, ftr);
@@ -356,7 +356,7 @@ static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
356356
val |= ftr;
357357

358358
vcpu_set_reg(vcpu, reg, val);
359-
vcpu_get_reg(vcpu, reg, &new_val);
359+
new_val = vcpu_get_reg(vcpu, reg);
360360
TEST_ASSERT_EQ(new_val, val);
361361

362362
return new_val;
@@ -370,7 +370,7 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
370370
uint64_t val, old_val, ftr;
371371
int r;
372372

373-
vcpu_get_reg(vcpu, reg, &val);
373+
val = vcpu_get_reg(vcpu, reg);
374374
ftr = (val & mask) >> shift;
375375

376376
ftr = get_invalid_value(ftr_bits, ftr);
@@ -384,7 +384,7 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
384384
TEST_ASSERT(r < 0 && errno == EINVAL,
385385
"Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
386386

387-
vcpu_get_reg(vcpu, reg, &val);
387+
val = vcpu_get_reg(vcpu, reg);
388388
TEST_ASSERT_EQ(val, old_val);
389389
}
390390

@@ -576,7 +576,7 @@ static void test_clidr(struct kvm_vcpu *vcpu)
576576
uint64_t clidr;
577577
int level;
578578

579-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), &clidr);
579+
clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1));
580580

581581
/* find the first empty level in the cache hierarchy */
582582
for (level = 1; level < 7; level++) {
@@ -601,7 +601,7 @@ static void test_ctr(struct kvm_vcpu *vcpu)
601601
{
602602
u64 ctr;
603603

604-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), &ctr);
604+
ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0));
605605
ctr &= ~CTR_EL0_DIC_MASK;
606606
if (ctr & CTR_EL0_IminLine_MASK)
607607
ctr--;
@@ -617,7 +617,7 @@ static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu)
617617
test_clidr(vcpu);
618618
test_ctr(vcpu);
619619

620-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), &val);
620+
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1));
621621
val++;
622622
vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_MPIDR_EL1), val);
623623

@@ -630,7 +630,7 @@ static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encodin
630630
size_t idx = encoding_to_range_idx(encoding);
631631
uint64_t observed;
632632

633-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding), &observed);
633+
observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding));
634634
TEST_ASSERT_EQ(test_reg_vals[idx], observed);
635635
}
636636

@@ -665,7 +665,7 @@ int main(void)
665665
vm = vm_create_with_one_vcpu(&vcpu, guest_code);
666666

667667
/* Check for AARCH64 only system */
668-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
668+
val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
669669
el0 = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), val);
670670
aarch64_only = (el0 == ID_AA64PFR0_EL1_ELx_64BIT_ONLY);
671671

‎tools/testing/selftests/kvm/aarch64/vpmu_counter_access.c

Lines changed: 9 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -440,8 +440,7 @@ static void create_vpmu_vm(void *guest_code)
440440
"Failed to create vgic-v3, skipping");
441441

442442
/* Make sure that PMUv3 support is indicated in the ID register */
443-
vcpu_get_reg(vpmu_vm.vcpu,
444-
KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1), &dfr0);
443+
dfr0 = vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1));
445444
pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), dfr0);
446445
TEST_ASSERT(pmuver != ID_AA64DFR0_EL1_PMUVer_IMP_DEF &&
447446
pmuver >= ID_AA64DFR0_EL1_PMUVer_IMP,
@@ -484,7 +483,7 @@ static void test_create_vpmu_vm_with_pmcr_n(uint64_t pmcr_n, bool expect_fail)
484483
create_vpmu_vm(guest_code);
485484
vcpu = vpmu_vm.vcpu;
486485

487-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), &pmcr_orig);
486+
pmcr_orig = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0));
488487
pmcr = pmcr_orig;
489488

490489
/*
@@ -493,7 +492,7 @@ static void test_create_vpmu_vm_with_pmcr_n(uint64_t pmcr_n, bool expect_fail)
493492
*/
494493
set_pmcr_n(&pmcr, pmcr_n);
495494
vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), pmcr);
496-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), &pmcr);
495+
pmcr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0));
497496

498497
if (expect_fail)
499498
TEST_ASSERT(pmcr_orig == pmcr,
@@ -521,7 +520,7 @@ static void run_access_test(uint64_t pmcr_n)
521520
vcpu = vpmu_vm.vcpu;
522521

523522
/* Save the initial sp to restore them later to run the guest again */
524-
vcpu_get_reg(vcpu, ARM64_CORE_REG(sp_el1), &sp);
523+
sp = vcpu_get_reg(vcpu, ARM64_CORE_REG(sp_el1));
525524

526525
run_vcpu(vcpu, pmcr_n);
527526

@@ -572,12 +571,12 @@ static void run_pmregs_validity_test(uint64_t pmcr_n)
572571
* Test if the 'set' and 'clr' variants of the registers
573572
* are initialized based on the number of valid counters.
574573
*/
575-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id), &reg_val);
574+
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id));
576575
TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,
577576
"Initial read of set_reg: 0x%llx has unimplemented counters enabled: 0x%lx",
578577
KVM_ARM64_SYS_REG(set_reg_id), reg_val);
579578

580-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id), &reg_val);
579+
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id));
581580
TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,
582581
"Initial read of clr_reg: 0x%llx has unimplemented counters enabled: 0x%lx",
583582
KVM_ARM64_SYS_REG(clr_reg_id), reg_val);
@@ -589,12 +588,12 @@ static void run_pmregs_validity_test(uint64_t pmcr_n)
589588
*/
590589
vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id), max_counters_mask);
591590

592-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id), &reg_val);
591+
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(set_reg_id));
593592
TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,
594593
"Read of set_reg: 0x%llx has unimplemented counters enabled: 0x%lx",
595594
KVM_ARM64_SYS_REG(set_reg_id), reg_val);
596595

597-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id), &reg_val);
596+
reg_val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(clr_reg_id));
598597
TEST_ASSERT((reg_val & (~valid_counters_mask)) == 0,
599598
"Read of clr_reg: 0x%llx has unimplemented counters enabled: 0x%lx",
600599
KVM_ARM64_SYS_REG(clr_reg_id), reg_val);
@@ -625,7 +624,7 @@ static uint64_t get_pmcr_n_limit(void)
625624
uint64_t pmcr;
626625

627626
create_vpmu_vm(guest_code);
628-
vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0), &pmcr);
627+
pmcr = vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0));
629628
destroy_vpmu_vm();
630629
return get_pmcr_n(pmcr);
631630
}

‎tools/testing/selftests/kvm/include/kvm_util.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -702,11 +702,13 @@ static inline int __vcpu_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t va
702702

703703
return __vcpu_ioctl(vcpu, KVM_SET_ONE_REG, &reg);
704704
}
705-
static inline void vcpu_get_reg(struct kvm_vcpu *vcpu, uint64_t id, void *addr)
705+
static inline uint64_t vcpu_get_reg(struct kvm_vcpu *vcpu, uint64_t id)
706706
{
707-
struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)addr };
707+
uint64_t val;
708+
struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)&val };
708709

709710
vcpu_ioctl(vcpu, KVM_GET_ONE_REG, &reg);
711+
return val;
710712
}
711713
static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val)
712714
{

‎tools/testing/selftests/kvm/lib/aarch64/processor.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -281,8 +281,8 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init)
281281
*/
282282
vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CPACR_EL1), 3 << 20);
283283

284-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_SCTLR_EL1), &sctlr_el1);
285-
vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TCR_EL1), &tcr_el1);
284+
sctlr_el1 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_SCTLR_EL1));
285+
tcr_el1 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_TCR_EL1));
286286

287287
/* Configure base granule size */
288288
switch (vm->mode) {
@@ -360,8 +360,8 @@ void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
360360
{
361361
uint64_t pstate, pc;
362362

363-
vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate), &pstate);
364-
vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc), &pc);
363+
pstate = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate));
364+
pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
365365

366366
fprintf(stream, "%*spstate: 0x%.16lx pc: 0x%.16lx\n",
367367
indent, "", pstate, pc);

‎tools/testing/selftests/kvm/lib/riscv/processor.c

Lines changed: 33 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -221,39 +221,39 @@ void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
221221
{
222222
struct kvm_riscv_core core;
223223

224-
vcpu_get_reg(vcpu, RISCV_CORE_REG(mode), &core.mode);
225-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc), &core.regs.pc);
226-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra), &core.regs.ra);
227-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp), &core.regs.sp);
228-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp), &core.regs.gp);
229-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp), &core.regs.tp);
230-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0), &core.regs.t0);
231-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1), &core.regs.t1);
232-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2), &core.regs.t2);
233-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0), &core.regs.s0);
234-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1), &core.regs.s1);
235-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0), &core.regs.a0);
236-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1), &core.regs.a1);
237-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2), &core.regs.a2);
238-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3), &core.regs.a3);
239-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4), &core.regs.a4);
240-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5), &core.regs.a5);
241-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6), &core.regs.a6);
242-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7), &core.regs.a7);
243-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2), &core.regs.s2);
244-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3), &core.regs.s3);
245-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4), &core.regs.s4);
246-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5), &core.regs.s5);
247-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6), &core.regs.s6);
248-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7), &core.regs.s7);
249-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8), &core.regs.s8);
250-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9), &core.regs.s9);
251-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10), &core.regs.s10);
252-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11), &core.regs.s11);
253-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3), &core.regs.t3);
254-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4), &core.regs.t4);
255-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5), &core.regs.t5);
256-
vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6), &core.regs.t6);
224+
core.mode = vcpu_get_reg(vcpu, RISCV_CORE_REG(mode));
225+
core.regs.pc = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.pc));
226+
core.regs.ra = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.ra));
227+
core.regs.sp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.sp));
228+
core.regs.gp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.gp));
229+
core.regs.tp = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.tp));
230+
core.regs.t0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t0));
231+
core.regs.t1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t1));
232+
core.regs.t2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t2));
233+
core.regs.s0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s0));
234+
core.regs.s1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s1));
235+
core.regs.a0 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a0));
236+
core.regs.a1 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a1));
237+
core.regs.a2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a2));
238+
core.regs.a3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a3));
239+
core.regs.a4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a4));
240+
core.regs.a5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a5));
241+
core.regs.a6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a6));
242+
core.regs.a7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.a7));
243+
core.regs.s2 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s2));
244+
core.regs.s3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s3));
245+
core.regs.s4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s4));
246+
core.regs.s5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s5));
247+
core.regs.s6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s6));
248+
core.regs.s7 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s7));
249+
core.regs.s8 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s8));
250+
core.regs.s9 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s9));
251+
core.regs.s10 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s10));
252+
core.regs.s11 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.s11));
253+
core.regs.t3 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t3));
254+
core.regs.t4 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t4));
255+
core.regs.t5 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t5));
256+
core.regs.t6 = vcpu_get_reg(vcpu, RISCV_CORE_REG(regs.t6));
257257

258258
fprintf(stream,
259259
" MODE: 0x%lx\n", core.mode);

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