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KVM: x86: Unpack F() CPUID feature flag macros to one flag per line of code
Refactor kvm_set_cpu_caps() to express each supported (or not) feature flag on a separate line, modulo a handful of cases where KVM does not, and likely will not, support a sequence of flags. This will allow adding fancier macros with longer, more descriptive names without resulting in absurd line lengths and/or weird code. Isolating each flag also makes it far easier to review changes, reduces code conflicts, and generally makes it easier to resolve conflicts. Lastly, it allows co-locating comments for notable flags, e.g. MONITOR, precisely with the relevant flag. No functional change intended. Suggested-by: Maxim Levitsky <mlevitsk@redhat.com> Link: https://lore.kernel.org/r/20241128013424.4096668-23-seanjc@google.com Signed-off-by: Sean Christopherson <seanjc@google.com>
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‎arch/x86/kvm/cpuid.c‎

Lines changed: 231 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -683,48 +683,121 @@ void kvm_set_cpu_caps(void)
683683
sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)));
684684

685685
kvm_cpu_cap_mask(CPUID_1_ECX,
686+
F(XMM3) |
687+
F(PCLMULQDQ) |
688+
0 /* DTES64 */ |
686689
/*
687690
* NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not*
688691
* advertised to guests via CPUID!
689692
*/
690-
F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
693+
0 /* MONITOR */ |
691694
0 /* DS-CPL, VMX, SMX, EST */ |
692-
0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
693-
F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) |
694-
F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
695-
F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
696-
0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
697-
F(F16C) | F(RDRAND)
695+
0 /* TM2 */ |
696+
F(SSSE3) |
697+
0 /* CNXT-ID */ |
698+
0 /* Reserved */ |
699+
F(FMA) |
700+
F(CX16) |
701+
0 /* xTPR Update */ |
702+
F(PDCM) |
703+
F(PCID) |
704+
0 /* Reserved, DCA */ |
705+
F(XMM4_1) |
706+
F(XMM4_2) |
707+
F(X2APIC) |
708+
F(MOVBE) |
709+
F(POPCNT) |
710+
0 /* Reserved*/ |
711+
F(AES) |
712+
F(XSAVE) |
713+
0 /* OSXSAVE */ |
714+
F(AVX) |
715+
F(F16C) |
716+
F(RDRAND)
698717
);
699718
/* KVM emulates x2apic in software irrespective of host support. */
700719
kvm_cpu_cap_set(X86_FEATURE_X2APIC);
701720

702721
kvm_cpu_cap_mask(CPUID_1_EDX,
703-
F(FPU) | F(VME) | F(DE) | F(PSE) |
704-
F(TSC) | F(MSR) | F(PAE) | F(MCE) |
705-
F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
706-
F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
707-
F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) |
708-
0 /* Reserved, DS, ACPI */ | F(MMX) |
709-
F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
722+
F(FPU) |
723+
F(VME) |
724+
F(DE) |
725+
F(PSE) |
726+
F(TSC) |
727+
F(MSR) |
728+
F(PAE) |
729+
F(MCE) |
730+
F(CX8) |
731+
F(APIC) |
732+
0 /* Reserved */ |
733+
F(SEP) |
734+
F(MTRR) |
735+
F(PGE) |
736+
F(MCA) |
737+
F(CMOV) |
738+
F(PAT) |
739+
F(PSE36) |
740+
0 /* PSN */ |
741+
F(CLFLUSH) |
742+
0 /* Reserved, DS, ACPI */ |
743+
F(MMX) |
744+
F(FXSR) |
745+
F(XMM) |
746+
F(XMM2) |
747+
F(SELFSNOOP) |
710748
0 /* HTT, TM, Reserved, PBE */
711749
);
712750

713751
kvm_cpu_cap_mask(CPUID_7_0_EBX,
714-
F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) |
715-
F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) |
716-
F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) |
717-
F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) |
718-
F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) |
719-
F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) |
752+
F(FSGSBASE) |
753+
F(SGX) |
754+
F(BMI1) |
755+
F(HLE) |
756+
F(AVX2) |
757+
F(FDP_EXCPTN_ONLY) |
758+
F(SMEP) |
759+
F(BMI2) |
760+
F(ERMS) |
761+
F(INVPCID) |
762+
F(RTM) |
763+
F(ZERO_FCS_FDS) |
764+
0 /*MPX*/ |
765+
F(AVX512F) |
766+
F(AVX512DQ) |
767+
F(RDSEED) |
768+
F(ADX) |
769+
F(SMAP) |
770+
F(AVX512IFMA) |
771+
F(CLFLUSHOPT) |
772+
F(CLWB) |
773+
0 /*INTEL_PT*/ |
774+
F(AVX512PF) |
775+
F(AVX512ER) |
776+
F(AVX512CD) |
777+
F(SHA_NI) |
778+
F(AVX512BW) |
720779
F(AVX512VL));
721780

722781
kvm_cpu_cap_mask(CPUID_7_ECX,
723-
F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) |
724-
F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) |
725-
F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) |
726-
F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ |
727-
F(SGX_LC) | F(BUS_LOCK_DETECT)
782+
F(AVX512VBMI) |
783+
F(LA57) |
784+
F(PKU) |
785+
0 /*OSPKE*/ |
786+
F(RDPID) |
787+
F(AVX512_VPOPCNTDQ) |
788+
F(UMIP) |
789+
F(AVX512_VBMI2) |
790+
F(GFNI) |
791+
F(VAES) |
792+
F(VPCLMULQDQ) |
793+
F(AVX512_VNNI) |
794+
F(AVX512_BITALG) |
795+
F(CLDEMOTE) |
796+
F(MOVDIRI) |
797+
F(MOVDIR64B) |
798+
0 /*WAITPKG*/ |
799+
F(SGX_LC) |
800+
F(BUS_LOCK_DETECT)
728801
);
729802
/* Set LA57 based on hardware capability. */
730803
if (cpuid_ecx(7) & feature_bit(LA57))
@@ -738,11 +811,22 @@ void kvm_set_cpu_caps(void)
738811
kvm_cpu_cap_clear(X86_FEATURE_PKU);
739812

740813
kvm_cpu_cap_mask(CPUID_7_EDX,
741-
F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) |
742-
F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) |
743-
F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) |
744-
F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) |
745-
F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D)
814+
F(AVX512_4VNNIW) |
815+
F(AVX512_4FMAPS) |
816+
F(SPEC_CTRL) |
817+
F(SPEC_CTRL_SSBD) |
818+
F(ARCH_CAPABILITIES) |
819+
F(INTEL_STIBP) |
820+
F(MD_CLEAR) |
821+
F(AVX512_VP2INTERSECT) |
822+
F(FSRM) |
823+
F(SERIALIZE) |
824+
F(TSXLDTRK) |
825+
F(AVX512_FP16) |
826+
F(AMX_TILE) |
827+
F(AMX_INT8) |
828+
F(AMX_BF16) |
829+
F(FLUSH_L1D)
746830
);
747831

748832
/* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */
@@ -759,50 +843,110 @@ void kvm_set_cpu_caps(void)
759843
kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD);
760844

761845
kvm_cpu_cap_mask(CPUID_7_1_EAX,
762-
F(SHA512) | F(SM3) | F(SM4) | F(AVX_VNNI) | F(AVX512_BF16) |
763-
F(CMPCCXADD) | F(FZRM) | F(FSRS) | F(FSRC) | F(AMX_FP16) |
764-
F(AVX_IFMA) | F(LAM)
846+
F(SHA512) |
847+
F(SM3) |
848+
F(SM4) |
849+
F(AVX_VNNI) |
850+
F(AVX512_BF16) |
851+
F(CMPCCXADD) |
852+
F(FZRM) |
853+
F(FSRS) |
854+
F(FSRC) |
855+
F(AMX_FP16) |
856+
F(AVX_IFMA) |
857+
F(LAM)
765858
);
766859

767860
kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX,
768-
F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(AMX_COMPLEX) |
769-
F(AVX_VNNI_INT16) | F(PREFETCHITI) | F(AVX10)
861+
F(AVX_VNNI_INT8) |
862+
F(AVX_NE_CONVERT) |
863+
F(AMX_COMPLEX) |
864+
F(AVX_VNNI_INT16) |
865+
F(PREFETCHITI) |
866+
F(AVX10)
770867
);
771868

772869
kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX,
773-
F(INTEL_PSFD) | F(IPRED_CTRL) | F(RRSBA_CTRL) | F(DDPD_U) |
774-
F(BHI_CTRL) | F(MCDT_NO)
870+
F(INTEL_PSFD) |
871+
F(IPRED_CTRL) |
872+
F(RRSBA_CTRL) |
873+
F(DDPD_U) |
874+
F(BHI_CTRL) |
875+
F(MCDT_NO)
775876
);
776877

777878
kvm_cpu_cap_mask(CPUID_D_1_EAX,
778-
F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd
879+
F(XSAVEOPT) |
880+
F(XSAVEC) |
881+
F(XGETBV1) |
882+
F(XSAVES) |
883+
f_xfd
779884
);
780885

781886
kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX,
782-
SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA)
887+
SF(SGX1) |
888+
SF(SGX2) |
889+
SF(SGX_EDECCSSA)
783890
);
784891

785892
kvm_cpu_cap_init_kvm_defined(CPUID_24_0_EBX,
786-
F(AVX10_128) | F(AVX10_256) | F(AVX10_512)
893+
F(AVX10_128) |
894+
F(AVX10_256) |
895+
F(AVX10_512)
787896
);
788897

789898
kvm_cpu_cap_mask(CPUID_8000_0001_ECX,
790-
F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ |
791-
F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
792-
F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) |
793-
0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) |
794-
F(TOPOEXT) | 0 /* PERFCTR_CORE */
899+
F(LAHF_LM) |
900+
F(CMP_LEGACY) |
901+
0 /*SVM*/ |
902+
0 /* ExtApicSpace */ |
903+
F(CR8_LEGACY) |
904+
F(ABM) |
905+
F(SSE4A) |
906+
F(MISALIGNSSE) |
907+
F(3DNOWPREFETCH) |
908+
F(OSVW) |
909+
0 /* IBS */ |
910+
F(XOP) |
911+
0 /* SKINIT, WDT, LWP */ |
912+
F(FMA4) |
913+
F(TBM) |
914+
F(TOPOEXT) |
915+
0 /* PERFCTR_CORE */
795916
);
796917

797918
kvm_cpu_cap_mask(CPUID_8000_0001_EDX,
798-
F(FPU) | F(VME) | F(DE) | F(PSE) |
799-
F(TSC) | F(MSR) | F(PAE) | F(MCE) |
800-
F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
801-
F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
802-
F(PAT) | F(PSE36) | 0 /* Reserved */ |
803-
F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
804-
F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) |
805-
0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW)
919+
F(FPU) |
920+
F(VME) |
921+
F(DE) |
922+
F(PSE) |
923+
F(TSC) |
924+
F(MSR) |
925+
F(PAE) |
926+
F(MCE) |
927+
F(CX8) |
928+
F(APIC) |
929+
0 /* Reserved */ |
930+
F(SYSCALL) |
931+
F(MTRR) |
932+
F(PGE) |
933+
F(MCA) |
934+
F(CMOV) |
935+
F(PAT) |
936+
F(PSE36) |
937+
0 /* Reserved */ |
938+
F(NX) |
939+
0 /* Reserved */ |
940+
F(MMXEXT) |
941+
F(MMX) |
942+
F(FXSR) |
943+
F(FXSR_OPT) |
944+
f_gbpages |
945+
F(RDTSCP) |
946+
0 /* Reserved */ |
947+
f_lm |
948+
F(3DNOWEXT) |
949+
F(3DNOW)
806950
);
807951

808952
if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64))
@@ -813,10 +957,18 @@ void kvm_set_cpu_caps(void)
813957
);
814958

815959
kvm_cpu_cap_mask(CPUID_8000_0008_EBX,
816-
F(CLZERO) | F(XSAVEERPTR) |
817-
F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) |
818-
F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) |
819-
F(AMD_PSFD) | F(AMD_IBPB_RET)
960+
F(CLZERO) |
961+
F(XSAVEERPTR) |
962+
F(WBNOINVD) |
963+
F(AMD_IBPB) |
964+
F(AMD_IBRS) |
965+
F(AMD_SSBD) |
966+
F(VIRT_SSBD) |
967+
F(AMD_SSB_NO) |
968+
F(AMD_STIBP) |
969+
F(AMD_STIBP_ALWAYS_ON) |
970+
F(AMD_PSFD) |
971+
F(AMD_IBPB_RET)
820972
);
821973

822974
/*
@@ -853,12 +1005,20 @@ void kvm_set_cpu_caps(void)
8531005
kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0);
8541006

8551007
kvm_cpu_cap_mask(CPUID_8000_001F_EAX,
856-
0 /* SME */ | 0 /* SEV */ | 0 /* VM_PAGE_FLUSH */ | 0 /* SEV_ES */ |
857-
F(SME_COHERENT));
1008+
0 /* SME */ |
1009+
0 /* SEV */ |
1010+
0 /* VM_PAGE_FLUSH */ |
1011+
0 /* SEV_ES */ |
1012+
F(SME_COHERENT)
1013+
);
8581014

8591015
kvm_cpu_cap_mask(CPUID_8000_0021_EAX,
860-
F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ |
861-
F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ |
1016+
F(NO_NESTED_DATA_BP) |
1017+
F(LFENCE_RDTSC) |
1018+
0 /* SmmPgCfgLock */ |
1019+
F(NULL_SEL_CLR_BASE) |
1020+
F(AUTOIBRS) |
1021+
0 /* PrefetchCtlMsr */ |
8621022
F(WRMSR_XX_BASE_NS)
8631023
);
8641024

@@ -887,9 +1047,16 @@ void kvm_set_cpu_caps(void)
8871047
kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR);
8881048

8891049
kvm_cpu_cap_mask(CPUID_C000_0001_EDX,
890-
F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) |
891-
F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) |
892-
F(PMM) | F(PMM_EN)
1050+
F(XSTORE) |
1051+
F(XSTORE_EN) |
1052+
F(XCRYPT) |
1053+
F(XCRYPT_EN) |
1054+
F(ACE2) |
1055+
F(ACE2_EN) |
1056+
F(PHE) |
1057+
F(PHE_EN) |
1058+
F(PMM) |
1059+
F(PMM_EN)
8931060
);
8941061

8951062
/*

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