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Merge pull request qemu#26 from yongbok/i6400-mips64r6-PRIP4
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Update core configurations P5600, I6400 and mips32r6-generic.
Fix cpu_mips_validate_access()

Closes qemu#23
Update for qemu#17

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
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@yongbok
yongbok committed Dec 23, 2014
2 parents cb44d12 + 4473b44 commit 27149d8
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Showing 2 changed files with 42 additions and 37 deletions.
2 changes: 1 addition & 1 deletion target-mips/helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -754,7 +754,7 @@ bool cpu_mips_validate_access(CPUMIPSState *env, target_ulong address,
int ret;
target_ulong addr;

addr = address & ~(data_size - 1);
addr = address & ~((target_ulong) data_size - 1);
ret = get_physical_address(env, &physical, &prot,
addr, rw, access_type);
if (ret != TLBRET_MATCH) {
Expand Down
77 changes: 41 additions & 36 deletions target-mips/translate_init.c
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Original file line number Diff line number Diff line change
Expand Up @@ -348,39 +348,43 @@ static const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000,
},
{
/* A generic CPU providing MIPS32 Release 5 features.
FIXME: Eventually this should be replaced by a real CPU model. */
.name = "mips32r5-generic",
.CP0_PRid = 0x00019700,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
.name = "P5600",
.CP0_PRid = 0x0001A820,
.CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x1 << CP0C0_AR) |
(MMU_TYPE_R4000 << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
(1 << CP0C1_CA),
.CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) |
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_FP),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
(1 << CP0C3_PW) | (1 << CP0C3_LPA) | (1 << CP0C3_PW),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_PW) |
(1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA),
.CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
(0x1C << CP0C4_KScrExist),
.CP0_Config4_rw_bitmask = 0,
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR) | (1 << CP0C5_LLB) |
(1 << CP0C5_MVH) | (1 << CP0C5_MRP),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) |
(1 << CP0C5_MRP) | (1 << CP0C5_UFR),
.CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
(1 << CP0C5_CV) | (0 << CP0C5_EVA) |
(1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
(1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFR) |
(0 << CP0C5_NFExists),
.CP0_PageGrain_rw_bitmask = 1 << CP0PG_ELPA,
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 4,
.SYNCI_Step = 32,
.CCRes = 2,
.CP0_Status_rw_bitmask = 0x3778FF1F,
.CP0_Status_rw_bitmask = 0x3C4AFF1F,
.CP0_PageGrain_rw_bitmask = (1 << CP0PG_RIE) | (1 << CP0PG_XIE) |
(1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
.CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
(0x93 << FCR0_PRID),
(0x03 << FCR0_PRID) | (0x20 << FCR0_REV),
.MSAIR = 0x03 << MSAIR_ProcID | 0x20 << MSAIR_Rev,
.SEGBITS = 32,
.PABITS = 40,
.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
.insn_flags = CPU_MIPS32R5 | ASE_MSA,
.mmu_type = MMU_TYPE_R4000,
},
{
Expand All @@ -397,12 +401,13 @@ static const mips_def_t mips_defs[] =
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) |
(1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M),
(1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_MSAP) |
(1U << CP0C3_M),
.CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
(3 << CP0C4_IE) | (1U << CP0C4_M),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB),
.CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
(1 << CP0C5_UFE),
(1 << CP0C5_UFE) | (1 << CP0C5_MSAEn),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 0,
.SYNCI_Step = 32,
Expand All @@ -416,7 +421,7 @@ static const mips_def_t mips_defs[] =
(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
.SEGBITS = 32,
.PABITS = 32,
.insn_flags = CPU_MIPS32R6,
.insn_flags = CPU_MIPS32R6 | ASE_MSA,
.mmu_type = MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)
Expand Down Expand Up @@ -556,26 +561,25 @@ static const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000,
},
{
/* A generic CPU supporting MIPS64 Release 6 ISA.
FIXME: Support IEEE 754-2008 FP.
Eventually this should be replaced by a real CPU model. */
.name = "MIPS64R6-generic",
.CP0_PRid = 0x00010000,
/* FIXME: Support IEEE 754-2008 FP and Virtual Core
*/
.name = "I6400",
.CP0_PRid = 0x0001A904,
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
(MMU_TYPE_R4000 << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (0x1F << CP0C1_MMU) |
(2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) |
(2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) |
(0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2,
.CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) |
(1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_LPA) |
(1U << CP0C3_M),
.CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) |
(1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
(1 << CP0C3_RXI) | (1 << CP0C3_LPA),
.CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
(3 << CP0C4_IE) | (1 << CP0C4_M),
(3 << CP0C4_IE) | (1U << CP0C4_M),
.CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_LLB),
.CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) |
(1 << CP0C5_UFE),
.CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 0,
.SYNCI_Step = 32,
Expand All @@ -586,10 +590,11 @@ static const mips_def_t mips_defs[] =
.CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA),
.CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_F64) | (1 << FCR0_L) |
(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
(0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
(0x03 << FCR0_PRID) | (0x20 << FCR0_REV),
.MSAIR = 0x03 << MSAIR_ProcID | 0x20 << MSAIR_Rev,
.SEGBITS = 42,
.PABITS = 48,
.insn_flags = CPU_MIPS64R6,
.insn_flags = CPU_MIPS64R6 | ASE_MSA,
.mmu_type = MMU_TYPE_R4000,
},
{
Expand Down

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