[VHDL] Fix VHDL implementation of bitwidth modifiers

[lucas-rami]

This commit replaces the Handshaking logic in the VHDL implementation of the bitwidth modifier entities trunc_op, sext_op, and zext_op. Previously, the ready signal was computed as a combination of the pValidArray (valid predecessor signal) and the nReadyArray (ready successor signal). While this works in most cases, it is too conservative and may cause deadlocks/critical path increases. As such, the ready signal is modified to just "forward" the dataflow successor's one. This makes the bitwidth modification components act as perfect "forwarders" of control signals, only altering the data signal in the process.