Skip to content
View laplaceyc's full-sized avatar
  • Synopsys Taiwan Co. Ltd.
  • Taiwan
Block or Report

Block or report laplaceyc

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. Hardware-Design-Lab Hardware-Design-Lab Public

    This repo is "NTHU Hardware Design & Lab" course project.

    Verilog 4 5

  2. Electronic-System-Level-Design Electronic-System-Level-Design Public

    This repo is "NTHU Electronic System Level Design" course project.

    Verilog 1 1

  3. Parallel-Programing Parallel-Programing Public

    This repo is "NTHU Parallel Programing" course project.

    C++ 11 2

  4. Physical-Design-Automation Physical-Design-Automation Public

    This repo is "NTHU Physical Design Automation" course project.

    Prolog 6

  5. VLSI-Testing VLSI-Testing Public

    This repo is "NTHU VLSI Testing" course project.

    Verilog 6

  6. VLSI_Design-Implementation VLSI_Design-Implementation Public

    This repo is "NTHU VLSI System Design and Implementation" course project.

    Verilog 11 3