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VTE is a library that allows fast and simple generation of C++ testers for modules written in Chisel and build an efficient interface to existing C++ based simulators. It contains Scala-based interface and C++ testbench class. Scala interface interacts with Firtl Interpreter and generates a basic set of C++ testbench files. These files contain the list of the Device Under Test (DUT) input-output ports as well as their parameters. C++ testbench provides functionalities similar to the Chisel PeekPokeTester, such as poke, expect, step functions. As a backend it uses Verilator.
Integration with existing system simulators written in C++, e.g. SST, gem5, BookSim, etc.
VTE is a library that allows fast and simple generation of C++ testers for modules written in Chisel and builds an efficient interface to existing C++ based simulators:
A. Scala-based Driver generates C++ Library (verilator APIs, DUT input/output bundles, testbench etc.)
B. Test file contains similar to chisel PeekPoke Test instructions
C. VTE generates the Makefile that automatically combines all generated files to create the executable
Anastasiia Butko (Lawrence Berkeley National Laboratory), Albert Chen (University of Berkeley, CA), Farzad Fatollahi-Fard, David Donofrio, John Shalf (Lawrence Berkeley National Laboratory)
Verilator Testbench Environment (VTE) Copyright (c) 2018, The Regents of the University of California, through Lawrence Berkeley National Laboratory (subject to receipt of any required approvals from the U.S. Dept. of Energy). All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
(1) Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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