Loop action

[leonardt]

Initial implementation of loop action for TBG, only tested on verilator.

Here's the generated main for test_tester_loop

 int main(int argc, char **argv) {
  Verilated::commandArgs(argc, argv);
  VArrayCircuit* top = new VArrayCircuit;

#if VM_TRACE
  Verilated::traceEverOn(true);
  tracer = new VerilatedVcdC;
  top->trace(tracer, 99);
  mkdir("logs", S_IRWXU | S_IRWXG | S_IROTH | S_IXOTH);
  tracer->open("logs/ArrayCircuit.vcd");
#endif

  top->I = 0;
  for (int __fault_loop_var_action_0 = 0; __fault_loop_var_action_0 < 7; __fault_loop_var_action_0++) {
      top->I = __fault_loop_var_action_0;
      top->eval();
      main_time++;
      #if VM_TRACE
      tracer->dump(main_time);
      #endif
      my_assert(top->O, __fault_loop_var_action_0, 1, "ArrayCircuit.O");
  }


#if VM_TRACE
  tracer->close();
#endif
}

[coveralls]

Pull Request Test Coverage Report for Build 794

• 42 of 56 (75.0%) changed or added relevant lines in 6 files are covered.
• 1 unchanged line in 1 file lost coverage.
• Overall coverage decreased (-0.07%) to 77.29%

---

Changes Missing Coverage	Covered Lines	Changed/Added Lines	%
fault/verilog_target.py	3	4	75.0%
fault/actions.py	10	12	83.33%
fault/cosa_target.py	1	5	20.0%
fault/system_verilog_target.py	1	8	12.5%

Files with Coverage Reduction	New Missed Lines	%
fault/verilog_target.py	1	88.1%

Totals
Change from base Build 770:	-0.07%
Covered Lines:	1249
Relevant Lines:	1616

---

💛 - Coveralls

[rsetaluri]

Very nice design. Few small comments

[rsetaluri]

hanging comment