Tap verilog #13
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Tap verilog #13
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…tagdriver and test
leonardt
requested changes
Oct 18, 2018
requirements.txt
Outdated
| @@ -5,3 +5,4 @@ git+git://github.com/phanrahan/mantle.git#egg=mantle | |||
| git+git://github.com/phanrahan/loam.git#egg=loam | |||
| coreir | |||
| git+git://github.com/leonardt/veriloggen.git#egg=veriloggen | |||
| git+git://github.com/leonardt/fault.git#egg=fault | |||
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Is this required? fault installation should be handled in setup.py
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@leonardt, I reverted the requirements.txt |
leonardt
approved these changes
Oct 19, 2018
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Looks good, thanks! At some point I may run this file through a processor to make it 4 space tabs. Not a blocking issue, but to keep the codebase consistent, it's nice to have every file follow the same style. (I know I'm an offender of inserting 4 space tabs in the 2 space tabs code base of coreir). But I'll defer the formatting to a tool which should make it easy to change (mainly just want to avoid merge conflicts from whitespace changes).
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It's been done, probably a good idea to get those changes ASAP if you plan to modify the file. |
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This PR contains TAP verilog along with a test which uses fault to test the verilog using a custom JTAG "driver"
Next step is to write a silica implementation of the tap fsm.