Tap

[leonardt]

Adds JTAG TAP controller example in Verilog and Silica. Accompanied by necessary internal changes to push the example through.

This is a basic version that uses just one yield statement, now the plan is to iterate on the coroutine representation to make it more compact (e.g. using loop patterns where possible).

First, I'd like to evaluate the quality of the synthesis results on this basic version (in theory, it should be identical to the verilog).

Good job all!

[coveralls]

Pull Request Test Coverage Report for Build 329

• 154 of 177 (87.01%) changed or added relevant lines in 12 files are covered.
• 45 unchanged lines in 7 files lost coverage.
• Overall coverage decreased (-0.1%) to 68.48%

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Changes Missing Coverage	Covered Lines	Changed/Added Lines	%
silica/cfg/util.py	16	17	94.12%
silica/cfg/ssa.py	38	41	92.68%
silica/width.py	6	15	40.0%
silica/transformations/promote_widths.py	18	28	64.29%

Files with Coverage Reduction	New Missed Lines	%
silica/transformations/promote_widths.py	1	65.31%
silica/cfg/ssa.py	2	81.08%
silica/cfg/control_flow_graph.py	3	65.63%
silica/width.py	3	45.71%
silica/compile.py	3	74.35%
silica/transformations/desugar_for_loops.py	12	60.2%
silica/verilog.py	21	70.05%

Totals
Change from base Build 290:	-0.1%
Covered Lines:	1662
Relevant Lines:	2427

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💛 - Coveralls

[rdaly525]

My guess is that the verilog might be bad due to the giant mux chain from the NS logic