-
Notifications
You must be signed in to change notification settings - Fork 1
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Initialize support for silica function translator #21
Conversation
Summary: Test Plan: Reviewers: Subscribers: Tasks: Tags: Blame Revision: Differential Revision: https://phabricator.intern.facebook.com/D13459938
Pull Request Test Coverage Report for Build 373
💛 - Coveralls |
Looks like a reasonable start to me - should we try to get this into magma rather than silica? It could be useful for circuit.combinational. |
Why do we need |
I think right now my plan is to keep any Python -> Verilog related code in silica since we have the verilog backend here already. If we move this to magma (which I'm not opposed to), we'll need to migrate a lot of code, so I think we should think/discuss the overall system/package/module architecture before investing in the migration. My initial thought is that a generic Python -> Verilog translator would be a useful tool for higher level DSLs being built on top of magma (Silica is just one instance of that), so that would motivate factoring this logic into magma or some other independent package. |
The |
This PR tracks an effort to provide support in the Silica compiler
for compiling pure Python functions to Verilog. This leverages
the existing Verilog backend used by the coroutine compiler
pipeline. There's still some work to clean up and organize how
we're doing this, but this serves as a minimum working example.