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This repository has been archived by the owner on Mar 18, 2020. It is now read-only.
GPIO 2 connected to ATTINY hardware reset chip (schematic pp 6)
GPIO2, 3 Designated as EJTAG_TDO, EJTAG_TMS
GPIO2, 3 connected to WAKE_L_0, WAKE_L_1 line on PCIe connectors. (schematic pp15)
Is there a conflict on GPIO 2??
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