coreboot-4.11: add fixes to KGPE-D16 raminit #1760
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The added patches fix bugs in fam15h ram DQS timing and configure the motherboard to restart gracefully if raminit fails instead of booting into an unstable state and/or crashing. Signed-off-by: Thierry Laurion <insurgo@riseup.net>
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Relative post under d16 club matrix room: https://matrix.to/#/!uNiXsBMseUsZDsZgDt:dodoid.com/$VfffoFicd5HtkQS5XP1_e2L6KidgZ4i6Un6754kvcMQ?via=dodoid.com&via=matrix.org&via=envs.net As per #692 current https://github.com/linuxboot/heads/blob/master/BOARD_TESTERS.md, tagging board owners interested into testing D16 builds, please report improvement/regressions here, I need at least one approval to merge, thank you. TESTING NEEDED: |
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So no observed regression on at least one supported HCL. Merging. |
| Subject: [PATCH 1/2] northbridge/amd: Fixed errors in fam15h DQS timing | ||
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| Fixed two errors in determining whether valid values were | ||
| found for read DQS delays in raminit. |
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Nice. As raminit is quite complex issue and a long known problem, as long as you have memory about your debugging and analysis, could you please elaborate. What was the problem? What type of RAM was affected? How can it be verified? What read DQS delay values were considered incorrect and are now correct?
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Nice. As raminit is quite complex issue and a long known problem, as long as you have memory about your debugging and analysis, could you please elaborate. What was the problem? What type of RAM was affected? How can it be verified? What read DQS delay values were considered incorrect and are now correct?
Three fixes are included in this patch that improve the reliability of raminit for all RAM.
- A logic error required only a single memory lane to pass DQS timing for read delays, this patch fixes it so all lanes must pass for the timing values to be added to the list of potential timing configurations.
- When raminit is searching for timing values, it now discards negative DQS values instead of adding the faulty parameters to the list of candidate configurations.
- Previously when raminit fails, coreboot continues to boot into an extremely unstable state (often resetting or freezing before coreboot can even finish booting). The patch just has the board reset and try again when raminit fails. This is a very lazy work around. After adding fixes 1&2, this patch only got triggered ~1 in 50 boots IIRC.
These patches improve the boot consistency. At times I'd have as many as 5 out of 10 boots fail under stock coreboot-4.11 (8xCT16G3ERSLD4160B, 2x6328), with these patches I had 1000+ boots without any issue. I do not know if these patches enable any new RAM configurations. It is possible that the "bad" RAM configs were more prone to incorrectly passing DQS timing with bad read delays (Fix 1). If that is the case, this could enable previously unusable RAM configs.
The added patches fix bugs in fam15h ram DQS timing and configure the motherboard to restart gracefully if raminit fails instead of booting into an unstable state and/or crashing.
Superseeds #1709 with signed commits to pass DCO from CI.