[Seq] Lower both registers and memories in the same pass

This PR moves the conversion of FIRRTL-specific `seq` ops to their own conversion pass, `SeqToSV`.
The existing register & memory lowering passes are packaged as re-usable utilities to keep them available as individual transformations.
Both the memory and register lowering utilities are packaged into a single parallelized lowering.

include/circt/Conversion/Passes.h

@@ -36,6 +36,7 @@
 #include "circt/Conversion/MooreToCore.h"
 #include "circt/Conversion/PipelineToHW.h"
 #include "circt/Conversion/SCFToCalyx.h"
+#include "circt/Conversion/SeqToSV.h"
 #include "circt/Conversion/StandardToHandshake.h"
 #include "circt/Conversion/VerifToSV.h"
 #include "mlir/IR/DialectRegistry.h"

include/circt/Conversion/Passes.td

@@ -652,4 +652,36 @@ def LowerArcToLLVM : Pass<"lower-arc-to-llvm", "mlir::ModuleOp"> {
   ];
 }
 
+//===----------------------------------------------------------------------===//
+// ConvertSeqToSV
+//===----------------------------------------------------------------------===//
+
+def LowerSeqFIRRTLToSV: Pass<"lower-seq-firrtl-to-sv",  "mlir::ModuleOp"> {
+  let summary = "Lower sequential firrtl ops to SV.";
+  let constructor = "circt::createSeqFIRRTLLowerToSVPass()";
+  let dependentDialects = ["circt::sv::SVDialect"];
+  let options = [
+    Option<"disableRegRandomization", "disable-reg-randomization", "bool", "false",
+           "Disable emission of register randomization code">,
+    Option<"emitSeparateAlwaysBlocks", "emit-separate-always-blocks", "bool", "false",
+           "Emit assigments to registers in separate always blocks">
+  ];
+  let statistics = [
+    Statistic<"numSubaccessRestored", "num-subaccess-restored",
+      "Number of lhs subaccess operations restored ">
+  ];
+}
+
+def LowerFirMem : Pass<"lower-seq-firmem", "mlir::ModuleOp"> {
+  let summary = "Lower seq.firmem ops to instances of hw.module.generated ops";
+  let constructor = "circt::createLowerFirMemPass()";
+  let dependentDialects = ["circt::hw::HWDialect"];
+}
+
+def LowerSeqFIRRTLInitToSV: Pass<"lower-seq-firrtl-init-to-sv", "mlir::ModuleOp"> {
+  let summary = "Prep the module with macro definitions for firrtl registers.";
+  let constructor = "circt::createLowerSeqFIRRTLInitToSV()";
+  let dependentDialects = ["circt::sv::SVDialect"];
+}
+
 #endif // CIRCT_CONVERSION_PASSES_TD

include/circt/Conversion/SeqToSV.h

@@ -0,0 +1,35 @@
+//===- SeqToSV.h - SV conversion for seq ops ----------------===-*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares passes which lower `seq` to `sv` and `hw`.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef CIRCT_CONVERSION_SEQTOSV_H
+#define CIRCT_CONVERSION_SEQTOSV_H
+
+#include "circt/Support/LLVM.h"
+#include <memory>
+
+namespace mlir {
+class Pass;
+} // namespace mlir
+
+namespace circt {
+
+#define GEN_PASS_DECL_LOWERSEQFIRRTLTOSV
+#include "circt/Conversion/Passes.h.inc"
+
+std::unique_ptr<mlir::Pass>
+createSeqFIRRTLLowerToSVPass(const LowerSeqFIRRTLToSVOptions &options = {});
+std::unique_ptr<mlir::Pass> createLowerFirMemPass();
+std::unique_ptr<mlir::Pass> createLowerSeqFIRRTLInitToSV();
+
+} // namespace circt
+
+#endif // CIRCT_CONVERSION_SEQTOSV_H

include/circt/Dialect/Seq/SeqPasses.h

@@ -20,19 +20,14 @@ namespace circt {
 namespace seq {
 
 #define GEN_PASS_DECL_LOWERSEQTOSV
-#define GEN_PASS_DECL_LOWERSEQFIRRTLTOSV
 #define GEN_PASS_DECL_EXTERNALIZECLOCKGATE
 #include "circt/Dialect/Seq/SeqPasses.h.inc"
 
 std::unique_ptr<mlir::Pass>
 createSeqLowerToSVPass(std::optional<bool> lowerToAlwaysFF = {});
-std::unique_ptr<mlir::Pass> createLowerSeqFIRRTLInitToSV();
-std::unique_ptr<mlir::Pass>
-createSeqFIRRTLLowerToSVPass(const LowerSeqFIRRTLToSVOptions &options = {});
 std::unique_ptr<mlir::Pass> createLowerSeqHLMemPass();
 std::unique_ptr<mlir::Pass>
 createExternalizeClockGatePass(const ExternalizeClockGateOptions &options = {});
-std::unique_ptr<mlir::Pass> createLowerFirMemPass();
 std::unique_ptr<mlir::Pass> createLowerSeqFIFOPass();
 
 /// Generate the code for registering passes.

include/circt/Dialect/Seq/SeqPasses.td

@@ -25,28 +25,6 @@ def LowerSeqToSV: Pass<"lower-seq-to-sv", "mlir::ModuleOp"> {
   ];
 }
 
-def LowerSeqFIRRTLInitToSV: Pass<"lower-seq-firrtl-init-to-sv", "mlir::ModuleOp"> {
-  let summary = "Prep the module with macro definitions for firrtl registers.";
-  let constructor = "circt::seq::createLowerSeqFIRRTLInitToSV()";
-  let dependentDialects = ["circt::sv::SVDialect"];
-}
-
-def LowerSeqFIRRTLToSV: Pass<"lower-seq-firrtl-to-sv",  "hw::HWModuleOp"> {
-  let summary = "Lower sequential firrtl ops to SV.";
-  let constructor = "circt::seq::createSeqFIRRTLLowerToSVPass()";
-  let dependentDialects = ["circt::sv::SVDialect"];
-  let options = [
-    Option<"disableRegRandomization", "disable-reg-randomization", "bool", "false",
-           "Disable emission of register randomization code">,
-    Option<"emitSeparateAlwaysBlocks", "emit-separate-always-blocks", "bool", "false",
-           "Emit assigments to registers in separate always blocks">
-  ];
-  let statistics = [
-    Statistic<"numSubaccessRestored", "num-subaccess-restored",
-      "Number of lhs subaccess operations restored ">
-  ];
-}
-
 def LowerSeqFIFO : Pass<"lower-seq-fifo", "hw::HWModuleOp"> {
   let summary = "Lower seq.fifo ops";
   let constructor = "circt::seq::createLowerSeqFIFOPass()";
@@ -83,10 +61,4 @@ def ExternalizeClockGate: Pass<"externalize-clock-gate", "mlir::ModuleOp"> {
   ];
 }
 
-def LowerFirMem : Pass<"lower-seq-firmem", "mlir::ModuleOp"> {
-  let summary = "Lower seq.firmem ops to instances of hw.module.generated ops";
-  let constructor = "circt::seq::createLowerFirMemPass()";
-  let dependentDialects = ["circt::hw::HWDialect"];
-}
-
 #endif // CIRCT_DIALECT_SEQ_SEQPASSES

lib/Conversion/CMakeLists.txt

@@ -10,17 +10,18 @@ add_subdirectory(ExportChiselInterface)
 add_subdirectory(ExportVerilog)
 add_subdirectory(FIRRTLToHW)
 add_subdirectory(FSMToSV)
-add_subdirectory(HandshakeToHW)
 add_subdirectory(HandshakeToDC)
+add_subdirectory(HandshakeToHW)
 add_subdirectory(HWArithToHW)
 add_subdirectory(HWToLLHD)
 add_subdirectory(HWToLLVM)
-add_subdirectory(HWToSystemC)
 add_subdirectory(HWToSV)
+add_subdirectory(HWToSystemC)
 add_subdirectory(LLHDToLLVM)
 add_subdirectory(LoopScheduleToCalyx)
 add_subdirectory(MooreToCore)
 add_subdirectory(PipelineToHW)
 add_subdirectory(SCFToCalyx)
+add_subdirectory(SeqToSV)
 add_subdirectory(StandardToHandshake)
 add_subdirectory(VerifToSV)

lib/Conversion/SeqToSV/CMakeLists.txt

@@ -0,0 +1,16 @@
+add_circt_conversion_library(CIRCTSeqToSV
+  FirMemLowering.cpp
+  FirRegLowering.cpp
+  SeqToSV.cpp
+  SeqFIRRTLInitToSV.cpp
+  LowerFirMem.cpp
+
+  DEPENDS
+  CIRCTConversionPassIncGen
+
+  LINK_COMPONENTS
+  Core
+
+  LINK_LIBS PUBLIC
+  CIRCTSeq
+)