[FIRRTL][CheckCombLoops] Cycle checking through references

[dtzSiFive]

References can be part of cycles, consider detecting such scenarios. Tools such as verilator (--lint-only) will flag this, example included at end.

Test input:

firrtl.circuit "Ref" {
  firrtl.module private @Send(in %val: !firrtl.uint<2>, out %x: !firrtl.ref<uint<2>>) {
    %ref_val = firrtl.ref.send %val : !firrtl.uint<2>
    firrtl.strictconnect %x, %ref_val : !firrtl.ref<uint<2>>
  }

  firrtl.module @Ref(out %x : !firrtl.uint<2>) {
    %sub_val, %sub_x = firrtl.instance sub @Send(in val: !firrtl.uint<2>, out x: !firrtl.ref<uint<2>>)
    %res = firrtl.ref.resolve %sub_x : !firrtl.ref<uint<2>>
    firrtl.connect %sub_val, %res : !firrtl.uint<2>, !firrtl.uint<2>
    firrtl.strictconnect %x, %sub_val : !firrtl.uint<2>
  }
}

Current output:

// Generated by CIRCT 1.31.0g20230217_f4a1235
module Send(	// ref-cycle.mlir:2:3
  input [1:0] val	// ref-cycle.mlir:2:34
);

endmodule

module Ref(	// ref-cycle.mlir:7:3
  output [1:0] x	// ref-cycle.mlir:7:26
);

  Send sub (	// ref-cycle.mlir:8:24
    .val (Ref.sub.val)	// ref-cycle.mlir:9:12, :10:5
  );
  assign x = Ref.sub.val;	// ref-cycle.mlir:7:3, :9:12, :10:5
endmodule

---

Verilator complaint, as mentioned (5.006):

%Error: ref-cycle.sv:13:6: Wire inputs its own output, creating circular logic (wire x=x)
   13 |     .val (Ref.sub.val)  
      |      ^~~
%Warning-UNOPTFLAT: ref-cycle.sv:3:15: Signal unoptimizable: Circular combinational logic: 'Ref.__Vcellinp__sub__val'
    3 |   input [1:0] val  
      |               ^~~
                    ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=5.006
                    ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
                    ref-cycle.sv:3:15:      Example path: Ref.__Vcellinp__sub__val
                    ref-cycle.sv:13:6:      Example path: ASSIGNW
                    ref-cycle.sv:3:15:      Example path: Ref.__Vcellinp__sub__val
%Error: Exiting due to 1 error(s), 1 warning(s)

[dtzSiFive]

Updated snippet for testing on recent firtool (1.42.0 presently):

firrtl.circuit "Ref" {
  firrtl.module private @Send(in %val: !firrtl.uint<2>, out %x: !firrtl.probe<uint<2>>) {
    %ref_val = firrtl.ref.send %val : !firrtl.uint<2>
    firrtl.ref.define %x, %ref_val : !firrtl.probe<uint<2>>
  }

  firrtl.module @Ref(out %x : !firrtl.uint<2>) {
    %sub_val, %sub_x = firrtl.instance sub @Send(in val: !firrtl.uint<2>, out x: !firrtl.probe<uint<2>>)
    %res = firrtl.ref.resolve %sub_x : !firrtl.probe<uint<2>>
    firrtl.connect %sub_val, %res : !firrtl.uint<2>, !firrtl.uint<2>
    firrtl.strictconnect %x, %sub_val : !firrtl.uint<2>
  }
}

[dtzSiFive]

Also should be sure to support:

• Forceable ref result
• ref.sub
• refcast
• ref-only loops

Working on this presently.