[FIRRTL] Introduce element-wise operations

[uenoku]

This PR introduces element-wise operations, firrrtl.elementwise_or, firrtl.elementwise_and and firrtl.elementwise_xor to represent logical operations over 1d vector types.

• FIRRTLOps -- type inference is added.
• Vectorization pass -- canonicalizer vector_create (a[0] or b[0], a[1] or b[1], a[2] or b[2], ...) -> elementwise_or a, b is added.
• LowerToHW -- elementwise_or a, b -> bitcast(comb.or (bitcast a), (bitcast b))

Example:

circuit Foo:
  module Foo:
    input a: UInt<3>[2]
    input b: UInt<3>[2]
    output c: UInt<3>[2][3]

    c[0][0] <= or(a[0], b[0])
    c[0][1] <= or(a[1], b[1])
    c[1][0] <= and(a[0], b[0])
    c[1][1] <= and(a[1], b[1])
    c[2][0] <= xor(a[0], b[0])
    c[2][1] <= xor(a[1], b[1])

firrtl.module @Foo(in %a: !firrtl.vector<uint<3>, 2>, in %b: !firrtl.vector<uint<3>, 2>, out %c_0: !firrtl.vector<uint<3>, 2>, out %c_1: !firrtl.vector<uint<3>, 2>, out %c_2: !firrtl.vector<uint<3>, 2>) {
  %0 = firrtl.elementwise_or %a, %b : (!firrtl.vector<uint<3>, 2>, !firrtl.vector<uint<3>, 2>) -> !firrtl.vector<uint<3>, 2>
  firrtl.strictconnect %c_0, %0 : !firrtl.vector<uint<3>, 2>
  %1 = firrtl.elementwise_and %a, %b : (!firrtl.vector<uint<3>, 2>, !firrtl.vector<uint<3>, 2>) -> !firrtl.vector<uint<3>, 2>
  firrtl.strictconnect %c_1, %1 : !firrtl.vector<uint<3>, 2>
  %2 = firrtl.elementwise_xor %a, %b : (!firrtl.vector<uint<3>, 2>, !firrtl.vector<uint<3>, 2>) -> !firrtl.vector<uint<3>, 2>
  firrtl.strictconnect %c_2, %2 : !firrtl.vector<uint<3>, 2>
}

module Foo(
  input  [1:0][2:0] a,
                    b,
  output [1:0][2:0] c_0,
                    c_1,
                    c_2
);

  wire [5:0] _GEN = /*cast(bit[5:0])*/a;
  wire [5:0] _GEN_0 = /*cast(bit[5:0])*/b;
  assign c_0 = /*cast(bit[1:0][2:0])*/_GEN | _GEN_0;
  assign c_1 = /*cast(bit[1:0][2:0])*/_GEN & _GEN_0;
  assign c_2 = /*ca

These temporary wires _GEN and _GEN_0 are unnecessary so ExportVerilog needs to be improved but probably we want to introduce vector operations to HW instead of relying on bitcast.

[uenoku]

• Separated the canonicalizer to Vectorization pass
• Added a test to lowertypes.

[darthscsi]

LGTM

[darthscsi]

I don't know that we need to promote this. I know you use it below, but it's not clear that you need to (see later comments)

[darthscsi]

Vector create isn't going to have a name, since it can't come from Chisel/FIRRTL.

[uenoku]

Vector create could have names if they are created by canonicalizing vector wires

[darthscsi]

Status?