[PipelineToHW] Don't CE pipeline regs in non-stallable pipelines

[mortbopet]

Will emit CompRegOp instead of CompRegClockEnabledOps for pipelines without stall signals.

In cases where a register has hierarchical clock gates specified (as in test_clockgates.mlir) but the "clock-gate-regs" option for lower-pipeline-to-hw is NOT set, then these hierarchical clock gates will be ignored.

[mortbopet]

This is where the option selection matrix is located:

circt/lib/Conversion/PipelineToHW/PipelineToHW.cpp

Lines 182 to 206 in 19146fe

	if (this->clockGateRegs) {
	// Use the clock gate instead of clock enable.
	Value currClockGate = notStalledClockGate;
	for (auto hierClockGateEnable :
	stageTerminator.getClockGatesForReg(regIdx)) {
	// Create clock gates for any hierarchically nested clock gates.
	currClockGate = builder.create<seq::ClockGateOp>(
	loc, currClockGate, hierClockGateEnable, /*test_enable=*/Value());
	}
	dataReg = builder.create<seq::CompRegOp>(stageTerminator->getLoc(),
	regIn, currClockGate, regName);
	} else {
	// Only clock-enable the register if the pipeline is stallable.
	// For non-stallable pipelines, a data register can always be clocked.
	if (hasStall) {
	dataReg = builder.create<seq::CompRegClockEnabledOp>(
	stageTerminator->getLoc(), regIn, args.clock,
	stageValidAndNotStalled, regName);
	} else {
	dataReg = builder.create<seq::CompRegOp>(stageTerminator->getLoc(),
	regIn, args.clock, regName);
	}
	}
	rets.regs.push_back(dataReg);
	}

[blakep-msft]

Looks good to me.

[teqdruid]

lgtm