[ExportVerilog] Bound type size considered for decl alignment #6171
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uenoku
approved these changes
Sep 22, 2023
dtzSiFive
approved these changes
Sep 22, 2023
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LGTM, but yes a strict-whitespace test would be nice.
Looks like this fixes the weird wrapping behavior bug when there's no decl word and it would "break" after the (empty) decl? Adding a regression test for that would be a good candidate for the test and something already have on-hand! 👍 .
We currently blindly align the types and names of declarations, which causes excessively large types like structs to ruin the alignment of declarations. Instead, introduce an upper bound above which a type does not contribute towards the `maxTypeWidth` count. This means that excessively large types are just emitted without alignment, without other declarations being forced to follow the same alignment. This change is purely cosmetic. Also tweak the code that emits the spacing around declarations to work by specifying a target column up to which spaces should be filled, and then filling in those spaces, or a minimum of 1. This makes it harder to get the alignment off by 1 just because some type or decl word was empty and didn't need a trailing space.
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Great point! I've added a check to the existing |
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Woohoo!! |
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We currently blindly align the types and names of declarations, which causes excessively large types like structs to ruin the alignment of declarations. Instead, introduce an upper bound above which a type does not contribute towards the
maxTypeWidthcount. This means that excessively large types are just emitted without alignment, without other declarations being forced to follow the same alignment. This change is purely cosmetic.Also tweak the code that emits the spacing around declarations to work by specifying a target column up to which spaces should be filled, and then filling in those spaces, or a minimum of 1. This makes it harder to get the alignment off by 1 just because some type or decl word was empty and didn't need a trailing space.