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nikicnikic
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[AMDGPU] Convert tests to opaque pointers (NFC)
1 parent 1d3d893 commit 00a4e24

26 files changed

+634
-634
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX11 %s
33
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX12 %s
44

5-
define amdgpu_kernel void @s_add_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
5+
define amdgpu_kernel void @s_add_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {
66
; GFX11-LABEL: s_add_u64:
77
; GFX11: ; %bb.0: ; %entry
88
; GFX11-NEXT: s_clause 0x1
@@ -35,11 +35,11 @@ define amdgpu_kernel void @s_add_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
3535
; GFX12-NEXT: s_endpgm
3636
entry:
3737
%add = add i64 %a, %b
38-
store i64 %add, i64 addrspace(1)* %out
38+
store i64 %add, ptr addrspace(1) %out
3939
ret void
4040
}
4141

42-
define amdgpu_ps void @v_add_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
42+
define amdgpu_ps void @v_add_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {
4343
; GCN-LABEL: v_add_u64:
4444
; GCN: ; %bb.0: ; %entry
4545
; GCN-NEXT: v_add_co_u32 v2, vcc_lo, v2, v4
@@ -50,11 +50,11 @@ define amdgpu_ps void @v_add_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
5050
; GCN-NEXT: s_endpgm
5151
entry:
5252
%add = add i64 %a, %b
53-
store i64 %add, i64 addrspace(1)* %out
53+
store i64 %add, ptr addrspace(1) %out
5454
ret void
5555
}
5656

57-
define amdgpu_kernel void @s_sub_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
57+
define amdgpu_kernel void @s_sub_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {
5858
; GFX11-LABEL: s_sub_u64:
5959
; GFX11: ; %bb.0: ; %entry
6060
; GFX11-NEXT: s_clause 0x1
@@ -87,11 +87,11 @@ define amdgpu_kernel void @s_sub_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
8787
; GFX12-NEXT: s_endpgm
8888
entry:
8989
%sub = sub i64 %a, %b
90-
store i64 %sub, i64 addrspace(1)* %out
90+
store i64 %sub, ptr addrspace(1) %out
9191
ret void
9292
}
9393

94-
define amdgpu_ps void @v_sub_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
94+
define amdgpu_ps void @v_sub_u64(ptr addrspace(1) %out, i64 %a, i64 %b) {
9595
; GCN-LABEL: v_sub_u64:
9696
; GCN: ; %bb.0: ; %entry
9797
; GCN-NEXT: v_sub_co_u32 v2, vcc_lo, v2, v4
@@ -102,6 +102,6 @@ define amdgpu_ps void @v_sub_u64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
102102
; GCN-NEXT: s_endpgm
103103
entry:
104104
%sub = sub i64 %a, %b
105-
store i64 %sub, i64 addrspace(1)* %out
105+
store i64 %sub, ptr addrspace(1) %out
106106
ret void
107107
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -327,8 +327,8 @@ body: |
327327
%ptr2:_(p1) = G_IMPLICIT_DEF
328328
%ptr3:_(p1) = COPY $vgpr2_vgpr3
329329
%ptr4:_(p1) = COPY $vgpr4_vgpr5
330-
G_STORE %src1:_(s32), %ptr1:_(p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
331-
G_STORE %src2:_(s32), %ptr2:_(p1) :: (volatile store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
330+
G_STORE %src1:_(s32), %ptr1:_(p1) :: (volatile store (s32) into `ptr addrspace(1) undef`, addrspace 1)
331+
G_STORE %src2:_(s32), %ptr2:_(p1) :: (volatile store (s32) into `ptr addrspace(1) undef`, addrspace 1)
332332
%div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
333333
G_STORE %div:_(s32), %ptr3:_(p1) :: (store (s32), addrspace 1, align 4)
334334
%rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll

Lines changed: 56 additions & 56 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll

Lines changed: 55 additions & 55 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AMDGPU/bf16.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2574,7 +2574,7 @@ define void @test_arg_store_v2bf16(<2 x bfloat> %in, ptr addrspace(1) %out) {
25742574
ret void
25752575
}
25762576

2577-
define void @test_arg_store_v3bf16(<3 x bfloat> %in, <3 x bfloat> addrspace(1)* %out) {
2577+
define void @test_arg_store_v3bf16(<3 x bfloat> %in, ptr addrspace(1) %out) {
25782578
; GCN-LABEL: test_arg_store_v3bf16:
25792579
; GCN: ; %bb.0:
25802580
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2637,7 +2637,7 @@ define void @test_arg_store_v3bf16(<3 x bfloat> %in, <3 x bfloat> addrspace(1)*
26372637
; GFX11-NEXT: global_store_b16 v[2:3], v1, off offset:4
26382638
; GFX11-NEXT: global_store_b32 v[2:3], v0, off
26392639
; GFX11-NEXT: s_setpc_b64 s[30:31]
2640-
store <3 x bfloat> %in, <3 x bfloat> addrspace(1) * %out
2640+
store <3 x bfloat> %in, ptr addrspace(1) %out
26412641
ret void
26422642
}
26432643

‎llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -15,25 +15,25 @@
1515

1616
--- |
1717

18-
define amdgpu_kernel void @long_branch_dbg_value(float addrspace(1)* nocapture %arg, float %arg1) #1 !dbg !5 {
18+
define amdgpu_kernel void @long_branch_dbg_value(ptr addrspace(1) nocapture %arg, float %arg1) #1 !dbg !5 {
1919
bb:
20-
%long_branch_dbg_value.kernarg.segment = call nonnull align 16 dereferenceable(12) i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
21-
%arg.kernarg.offset = getelementptr inbounds i8, i8 addrspace(4)* %long_branch_dbg_value.kernarg.segment, i64 0
22-
%arg.kernarg.offset.cast = bitcast i8 addrspace(4)* %arg.kernarg.offset to float addrspace(1)* addrspace(4)*, !amdgpu.uniform !2, !amdgpu.noclobber !2
23-
%arg.load = load float addrspace(1)*, float addrspace(1)* addrspace(4)* %arg.kernarg.offset.cast, align 16, !invariant.load !2
24-
%arg1.kernarg.offset = getelementptr inbounds i8, i8 addrspace(4)* %long_branch_dbg_value.kernarg.segment, i64 8
25-
%arg1.kernarg.offset.cast = bitcast i8 addrspace(4)* %arg1.kernarg.offset to float addrspace(4)*, !amdgpu.uniform !2, !amdgpu.noclobber !2
26-
%arg1.load = load float, float addrspace(4)* %arg1.kernarg.offset.cast, align 8, !invariant.load !2
20+
%long_branch_dbg_value.kernarg.segment = call nonnull align 16 dereferenceable(12) ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
21+
%arg.kernarg.offset = getelementptr inbounds i8, ptr addrspace(4) %long_branch_dbg_value.kernarg.segment, i64 0
22+
%arg.kernarg.offset.cast = bitcast ptr addrspace(4) %arg.kernarg.offset to ptr addrspace(4), !amdgpu.uniform !2, !amdgpu.noclobber !2
23+
%arg.load = load ptr addrspace(1), ptr addrspace(4) %arg.kernarg.offset.cast, align 16, !invariant.load !2
24+
%arg1.kernarg.offset = getelementptr inbounds i8, ptr addrspace(4) %long_branch_dbg_value.kernarg.segment, i64 8
25+
%arg1.kernarg.offset.cast = bitcast ptr addrspace(4) %arg1.kernarg.offset to ptr addrspace(4), !amdgpu.uniform !2, !amdgpu.noclobber !2
26+
%arg1.load = load float, ptr addrspace(4) %arg1.kernarg.offset.cast, align 8, !invariant.load !2
2727
%tmp = fmul float %arg1.load, %arg1.load
28-
%tmp2 = getelementptr inbounds float, float addrspace(1)* %arg.load, i64 3
29-
call void @llvm.dbg.value(metadata float addrspace(1)* %tmp2, metadata !11, metadata !DIExpression()) #5, !dbg !12
30-
store float %tmp, float addrspace(1)* %tmp2, align 4, !dbg !12
28+
%tmp2 = getelementptr inbounds float, ptr addrspace(1) %arg.load, i64 3
29+
call void @llvm.dbg.value(metadata ptr addrspace(1) %tmp2, metadata !11, metadata !DIExpression()) #5, !dbg !12
30+
store float %tmp, ptr addrspace(1) %tmp2, align 4, !dbg !12
3131
%tmp3 = fcmp olt float %tmp, 0x3810000000000000
3232
%tmp3.inv = xor i1 %tmp3, true
3333
br i1 %tmp3.inv, label %bb4, label %bb8, !amdgpu.uniform !2
3434

3535
bb4: ; preds = %bb
36-
%tmp5 = load volatile float, float addrspace(1)* undef, align 4
36+
%tmp5 = load volatile float, ptr addrspace(1) undef, align 4
3737
%tmp6 = fcmp oeq float %tmp5, 0x7FF0000000000000
3838
br i1 %tmp6, label %bb7, label %Flow, !amdgpu.uniform !2
3939

@@ -47,7 +47,7 @@
4747
ret void
4848
}
4949

50-
declare align 4 i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2
50+
declare align 4 ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #2
5151
declare void @llvm.dbg.value(metadata, metadata, metadata) #0
5252

5353
attributes #0 = { nounwind readnone speculatable willreturn }
@@ -103,7 +103,7 @@ body: |
103103
renamable $sgpr4_sgpr5 = IMPLICIT_DEF
104104
$vgpr0 = V_MOV_B32_e32 $sgpr4, implicit $exec, implicit-def $vgpr0_vgpr1, implicit $sgpr4_sgpr5
105105
$vgpr1 = V_MOV_B32_e32 $sgpr5, implicit $exec, implicit killed $sgpr4_sgpr5, implicit $exec
106-
renamable $vgpr0 = GLOBAL_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec :: (volatile load (s32) from `float addrspace(1)* undef`, addrspace 1)
106+
renamable $vgpr0 = GLOBAL_LOAD_DWORD killed renamable $vgpr0_vgpr1, 0, 0, implicit $exec :: (volatile load (s32) from `ptr addrspace(1) undef`, addrspace 1)
107107
renamable $sgpr4 = S_MOV_B32 2139095040
108108
S_WAITCNT 3952
109109
renamable $sgpr4_sgpr5 = nofpexcept V_CMP_NEQ_F32_e64 0, killed $sgpr4, 0, killed $vgpr0, 0, implicit $mode, implicit $exec

‎llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1385,7 +1385,7 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned(ptr addrspace(1) noalias
13851385

13861386
; The other use of shuffle0_0 make it profitable to lower into v_perm
13871387

1388-
define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned_multiuse(<4 x float> addrspace(1)* noalias %out, <4 x i8> addrspace(1)* noalias %out1, <4 x i8> addrspace(1)* noalias %in, <4 x i8> addrspace(1)* noalias %in1) nounwind {
1388+
define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned_multiuse(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %out1, ptr addrspace(1) noalias %in, ptr addrspace(1) noalias %in1) nounwind {
13891389
; SI-LABEL: load_v4i8_to_v4f32_unaligned_multiuse:
13901390
; SI: ; %bb.0:
13911391
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
@@ -1547,14 +1547,14 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned_multiuse(<4 x float> add
15471547
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
15481548
; GFX11-NEXT: s_endpgm
15491549
%tid = call i32 @llvm.amdgcn.workitem.id.x()
1550-
%gep = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in, i32 %tid
1551-
%gep1 = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %in1, i32 %tid
1552-
%load = load <4 x i8>, <4 x i8> addrspace(1)* %gep, align 1
1553-
%load1 = load <4 x i8>, <4 x i8> addrspace(1)* %gep1, align 1
1550+
%gep = getelementptr <4 x i8>, ptr addrspace(1) %in, i32 %tid
1551+
%gep1 = getelementptr <4 x i8>, ptr addrspace(1) %in1, i32 %tid
1552+
%load = load <4 x i8>, ptr addrspace(1) %gep, align 1
1553+
%load1 = load <4 x i8>, ptr addrspace(1) %gep1, align 1
15541554
%shuffle0_0 = shufflevector <4 x i8> %load, <4 x i8> %load1, <4 x i32> <i32 3, i32 2, i32 6, i32 2>
15551555
%cvt = uitofp <4 x i8> %shuffle0_0 to <4 x float>
1556-
store <4 x float> %cvt, <4 x float> addrspace(1)* %out, align 16
1557-
store <4 x i8> %shuffle0_0, <4 x i8> addrspace(1)* %out1, align 4
1556+
store <4 x float> %cvt, ptr addrspace(1) %out, align 16
1557+
store <4 x i8> %shuffle0_0, ptr addrspace(1) %out1, align 4
15581558
ret void
15591559
}
15601560

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2b.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck -check-prefix=GCN %s
33

44
--- |
5-
define amdgpu_kernel void @single-wave-phase-2b(i32 addrspace(3)* noalias %in0, i32 addrspace(3)* noalias %in1, i32 addrspace(3)* noalias %in2, i32 addrspace(3)* noalias %in3, i32 addrspace(3)* noalias %in4, i32 addrspace(3)* noalias %in5, i32 addrspace(3)* noalias %in6, i32 addrspace(3)* noalias %in7, i32 addrspace(3)* noalias %in8, i32 addrspace(3)* noalias %in9, i32 addrspace(3)* noalias %in10, i32 addrspace(3)* noalias %in11, i32 addrspace(7)* noalias %in12, i32 addrspace(7)* noalias %in13, i32 addrspace(7)* noalias %in14, i32 addrspace(7)* noalias %in15, i32 addrspace(7)* noalias %in16, i32 addrspace(7)* noalias %in17, i32 addrspace(7)* noalias %in18, i32 addrspace(7)* noalias %in19, i32 addrspace(7)* noalias %in20, i32 addrspace(7)* noalias %in21, i32 addrspace(7)* noalias %in22, i32 addrspace(7)* noalias %in23, i32 addrspace(7)* noalias %in24, i32 addrspace(7)* noalias %in25, i32 addrspace(7)* noalias %in26, i32 addrspace(7)* noalias %in27, i32 addrspace(7)* noalias %in28, i32 addrspace(7)* noalias %in29) #0 { ret void }
5+
define amdgpu_kernel void @single-wave-phase-2b(ptr addrspace(3) noalias %in0, ptr addrspace(3) noalias %in1, ptr addrspace(3) noalias %in2, ptr addrspace(3) noalias %in3, ptr addrspace(3) noalias %in4, ptr addrspace(3) noalias %in5, ptr addrspace(3) noalias %in6, ptr addrspace(3) noalias %in7, ptr addrspace(3) noalias %in8, ptr addrspace(3) noalias %in9, ptr addrspace(3) noalias %in10, ptr addrspace(3) noalias %in11, ptr addrspace(7) noalias %in12, ptr addrspace(7) noalias %in13, ptr addrspace(7) noalias %in14, ptr addrspace(7) noalias %in15, ptr addrspace(7) noalias %in16, ptr addrspace(7) noalias %in17, ptr addrspace(7) noalias %in18, ptr addrspace(7) noalias %in19, ptr addrspace(7) noalias %in20, ptr addrspace(7) noalias %in21, ptr addrspace(7) noalias %in22, ptr addrspace(7) noalias %in23, ptr addrspace(7) noalias %in24, ptr addrspace(7) noalias %in25, ptr addrspace(7) noalias %in26, ptr addrspace(7) noalias %in27, ptr addrspace(7) noalias %in28, ptr addrspace(7) noalias %in29) #0 { ret void }
66

77
!0 = distinct !{!0}
88
!1 = !{!1, !0}

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -run-pass=machine-scheduler -verify-misched -o - %s | FileCheck -check-prefix=GCN %s
33

44
--- |
5-
define amdgpu_kernel void @single-wave-phase-2c(i32 addrspace(3)* noalias %in0, i32 addrspace(3)* noalias %in1, i32 addrspace(3)* noalias %in2, i32 addrspace(3)* noalias %in3, i32 addrspace(3)* noalias %in4, i32 addrspace(3)* noalias %in5, i32 addrspace(3)* noalias %in6, i32 addrspace(3)* noalias %in7, i32 addrspace(3)* noalias %in8, i32 addrspace(3)* noalias %in9, i32 addrspace(3)* noalias %in10, i32 addrspace(3)* noalias %in11, i32 addrspace(7)* noalias %in12, i32 addrspace(7)* noalias %in13, i32 addrspace(7)* noalias %in14, i32 addrspace(7)* noalias %in15, i32 addrspace(7)* noalias %in16, i32 addrspace(7)* noalias %in17) #0 { ret void }
5+
define amdgpu_kernel void @single-wave-phase-2c(ptr addrspace(3) noalias %in0, ptr addrspace(3) noalias %in1, ptr addrspace(3) noalias %in2, ptr addrspace(3) noalias %in3, ptr addrspace(3) noalias %in4, ptr addrspace(3) noalias %in5, ptr addrspace(3) noalias %in6, ptr addrspace(3) noalias %in7, ptr addrspace(3) noalias %in8, ptr addrspace(3) noalias %in9, ptr addrspace(3) noalias %in10, ptr addrspace(3) noalias %in11, ptr addrspace(7) noalias %in12, ptr addrspace(7) noalias %in13, ptr addrspace(7) noalias %in14, ptr addrspace(7) noalias %in15, ptr addrspace(7) noalias %in16, ptr addrspace(7) noalias %in17) #0 { ret void }
66

77

88
!0 = distinct !{!0}

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -176,10 +176,10 @@ define amdgpu_kernel void @safe_rsq_rcp_pat_f64(ptr addrspace(1) %out, double %s
176176
; SI-NOT: v_rsq_f64_e32
177177
; SI: v_sqrt_f64
178178
; SI: v_rcp_f64
179-
define amdgpu_kernel void @safe_amdgcn_sqrt_rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) #1 {
179+
define amdgpu_kernel void @safe_amdgcn_sqrt_rsq_rcp_pat_f64(ptr addrspace(1) %out, double %src) #1 {
180180
%sqrt = call double @llvm.amdgcn.sqrt.f64(double %src)
181181
%rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt)
182-
store double %rcp, double addrspace(1)* %out, align 8
182+
store double %rcp, ptr addrspace(1) %out, align 8
183183
ret void
184184
}
185185

@@ -195,10 +195,10 @@ define amdgpu_kernel void @safe_amdgcn_sqrt_rsq_rcp_pat_f64(double addrspace(1)*
195195
; SI: v_fma_f64
196196
; SI: v_rcp_f64
197197
; SI: buffer_store_dwordx2
198-
define amdgpu_kernel void @unsafe_rsq_rcp_pat_f64(double addrspace(1)* %out, double %src) #2 {
198+
define amdgpu_kernel void @unsafe_rsq_rcp_pat_f64(ptr addrspace(1) %out, double %src) #2 {
199199
%sqrt = call double @llvm.sqrt.f64(double %src)
200200
%rcp = call double @llvm.amdgcn.rcp.f64(double %sqrt)
201-
store double %rcp, double addrspace(1)* %out, align 8
201+
store double %rcp, ptr addrspace(1) %out, align 8
202202
ret void
203203
}
204204

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