[Power10] Enable the heuristic for Power10 and switch the sched model

QingShan Zhang · QingShan Zhang · commit 0680a3d56d8b · 2020-09-12T02:49:47.000Z
with P9 Model Enable the pre-ra and post-ra scheduler strategy for Power10 as we want to customize the heuristic later. And switch the scheduler model with P9 model before P10 Model is available. The NoSchedModel is modelled as in-order cpu and the pre-ra scheduler is not bi-directional which will have big impact on the scheduler. Reviewed By: jji Differential Revision: https://reviews.llvm.org/D86865
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
@@ -325,6 +325,8 @@ def ProcessorFeatures {
     [DirectivePwr9,
      FeatureP9Altivec,
      FeatureP9Vector,
+     FeaturePPCPreRASched,
+     FeaturePPCPostRASched,
      FeatureISA3_0,
      FeaturePredictableSelectIsExpensive
     ];
@@ -334,9 +336,7 @@ def ProcessorFeatures {
   // dispatch for vector operations than scalar ones. For the time being,
   // this list also includes scheduling-related features since we do not have
   // enough info to create custom scheduling strategies for future CPUs.
-  list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits,
-                                               FeaturePPCPreRASched,
-                                               FeaturePPCPostRASched];
+  list<SubtargetFeature> P9SpecificFeatures = [FeatureVectorsUseTwoUnits];
   list<SubtargetFeature> P9InheritableFeatures =
     !listconcat(P8InheritableFeatures, P9AdditionalFeatures);
   list<SubtargetFeature> P9Features =
@@ -559,7 +559,7 @@ def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
 def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
 // No scheduler model yet.
-def : ProcessorModel<"pwr10", NoSchedModel, ProcessorFeatures.P10Features>;
+def : ProcessorModel<"pwr10", P9Model, ProcessorFeatures.P10Features>;
 // No scheduler model for future CPU.
 def : ProcessorModel<"future", NoSchedModel,
                   ProcessorFeatures.FutureFeatures>;
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll
@@ -45,12 +45,12 @@ define dso_local signext i32 @AsmClobberX2WithTOC(i32 signext %a, i32 signext %b
 ; CHECK-LARGE:     ld r2, .Lfunc_toc2-.Lfunc_gep2(r12)
 ; CHECK-LARGE:     add r2, r2, r12
 ; CHECK-S:         .localentry     AsmClobberX2WithTOC
-; CHECK-S:         #APP
+; CHECK-S:         add r3, r4, r3
+; CHECK-S-NEXT:    #APP
 ; CHECK-S-NEXT:    li r2, 0
 ; CHECK-S-NEXT:    #NO_APP
-; CHECK-S-NEXT:    plwz r5, global_int@PCREL(0), 1
-; CHECK-S-NEXT:    add r3, r4, r3
-; CHECK-S-NEXT:    add r3, r3, r5
+; CHECK-S-NEXT:    plwz r4, global_int@PCREL(0), 1
+; CHECK-S-NEXT:    add r3, r3, r4
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    blr
 entry:
@@ -67,10 +67,10 @@ define dso_local signext i32 @AsmClobberX5(i32 signext %a, i32 signext %b) local
 ; CHECK-P9-NOT:    .localentry
 ; CHECK-ALL:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    add r3, r4, r3
-; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    #APP
 ; CHECK-S-NEXT:    nop
 ; CHECK-S-NEXT:    #NO_APP
+; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    blr
 entry:
   %add = add nsw i32 %b, %a
@@ -109,24 +109,24 @@ define dso_local signext i32 @X2IsCallerSaved(i32 signext %a, i32 signext %b, i3
 ; CHECK-S-NEXT:    add r9, r10, r9
 ; CHECK-S-NEXT:    sub r10, r10, r3
 ; CHECK-S-NEXT:    mullw r3, r4, r3
+; CHECK-S-NEXT:    sub r12, r4, r5
+; CHECK-S-NEXT:    add r0, r6, r5
+; CHECK-S-NEXT:    sub r2, r6, r7
+; CHECK-S-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
+; CHECK-S-NEXT:    add r30, r8, r7
 ; CHECK-S-NEXT:    mullw r3, r3, r11
 ; CHECK-S-NEXT:    mullw r3, r3, r5
-; CHECK-S-NEXT:    sub r12, r4, r5
 ; CHECK-S-NEXT:    mullw r3, r3, r6
-; CHECK-S-NEXT:    add r0, r6, r5
 ; CHECK-S-NEXT:    mullw r3, r3, r12
 ; CHECK-S-NEXT:    mullw r3, r3, r0
 ; CHECK-S-NEXT:    mullw r3, r3, r7
-; CHECK-S-NEXT:    sub r2, r6, r7
 ; CHECK-S-NEXT:    mullw r3, r3, r8
-; CHECK-S-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-S-NEXT:    add r30, r8, r7
 ; CHECK-S-NEXT:    mullw r3, r3, r2
 ; CHECK-S-NEXT:    mullw r3, r3, r30
-; CHECK-S-NEXT:    mullw r3, r3, r29
-; CHECK-S-NEXT:    mullw r3, r3, r9
 ; CHECK-S-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
+; CHECK-S-NEXT:    mullw r3, r3, r29
 ; CHECK-S-NEXT:    ld r29, -24(r1) # 8-byte Folded Reload
+; CHECK-S-NEXT:    mullw r3, r3, r9
 ; CHECK-S-NEXT:    mullw r3, r3, r10
 ; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    blr
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll b/llvm/test/CodeGen/PowerPC/pcrel-call-linkage-with-calls.ll
@@ -353,10 +353,10 @@ define dso_local signext i32 @IndirectCall3(i32 signext %a, i32 signext %b, i32
 ; CHECK-S-NEXT:    stdu r1, -32(r1)
 ; CHECK-S-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-S-NEXT:    .cfi_offset lr, 16
-; CHECK-S-NEXT:    add r3, r4, r3
-; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    mtctr r5
+; CHECK-S-NEXT:    add r3, r4, r3
 ; CHECK-S-NEXT:    mr r12, r5
+; CHECK-S-NEXT:    extsw r3, r3
 ; CHECK-S-NEXT:    bctrl
 ; CHECK-S-NEXT:    plwz r4, globalVar@PCREL(0), 1
 ; CHECK-S-NEXT:    mullw r3, r4, r3
diff --git a/llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll b/llvm/test/CodeGen/PowerPC/pcrel-tail-calls.ll
@@ -185,8 +185,8 @@ define dso_local signext i32 @TailCallAbs() local_unnamed_addr {
 ; CHECK:         .localentry TailCallAbs, 1
 ; CHECK-NEXT:  # %bb.0: # %entry
 ; CHECK-NEXT:    li r3, 400
-; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r12, 400
+; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    bctr
 ; CHECK-NEXT:    #TC_RETURNr8 ctr 0
 entry:
@@ -207,8 +207,8 @@ define dso_local signext i32 @NoTailCallAbs(i32 signext %a) local_unnamed_addr {
 ; CHECK-NEXT:    stdu r1, -48(r1)
 ; CHECK-NEXT:    mr r30, r3
 ; CHECK-NEXT:    li r3, 400
-; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    li r12, 400
+; CHECK-NEXT:    mtctr r3
 ; CHECK-NEXT:    bctrl
 ; CHECK-NEXT:    add r3, r3, r30
 ; CHECK-NEXT:    extsw r3, r3
